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Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-07-27 20:29:48 +00:00
parent 772fe17a6d
commit 06470311c5
2 changed files with 31 additions and 2 deletions
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32
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2090,22 +2090,50 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
// STRT, STRBT, and STRHT are for disassembly only. // STRT, STRBT, and STRHT are for disassembly only.
def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr), def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, ldst_so_reg:$addr),
IndexModePost, StFrm, IIC_iStore_ru, IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{25} = 1;
let Inst{21} = 1; // overwrite
let Inst{4} = 0;
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
}
def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addrmode_imm12:$addr),
IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{25} = 0;
let Inst{21} = 1; // overwrite let Inst{21} = 1; // overwrite
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
} }
def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, ldst_so_reg:$addr),
IndexModePost, StFrm, IIC_iStore_bh_ru, IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb", "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{25} = 1;
let Inst{21} = 1; // overwrite
let Inst{4} = 0;
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
}
def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addrmode_imm12:$addr),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{25} = 0;
let Inst{21} = 1; // overwrite let Inst{21} = 1; // overwrite
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
} }
def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr), def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
StMiscFrm, IIC_iStore_bh_ru, StMiscFrm, IIC_iStore_bh_ru,
"strht", "\t$Rt, $addr", "$addr.base = $base_wb", "strht", "\t$Rt, $addr", "$addr.base = $base_wb",

1
test/MC/ARM/arm_addrmode2.s
View File

@ -1,4 +1,5 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
@ XFAIL: *
@ Post-indexed @ Post-indexed
@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]