From 0648ccf1e99b2748144f736e1ab89c935fd6f6f7 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 28 Sep 2005 22:38:27 +0000 Subject: [PATCH] Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but not associative. Add [SU]REM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23508 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrInfo.td | 38 ++++++++++++++++++------------ 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 9467f17cd5d..719968db6e6 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -65,14 +65,14 @@ class SDTypeProfile]>; // for 'imm'. -def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt' -def SDTBinOp : SDTypeProfile<1, 2, [ // add, mul, etc. - SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> -]>; -def SDTIntBinOp : SDTypeProfile<1, 2, [ // and, or, xor, udiv, etc. +def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. +def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt' +def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; +def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> +]>; def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz SDTCisSameAs<0, 1>, SDTCisInt<0> ]>; @@ -106,21 +106,29 @@ def node; def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">; +def add : SDNode<"ISD::ADD" , SDTIntBinOp , + [SDNPCommutative, SDNPAssociative]>; +def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; +def mul : SDNode<"ISD::MUL" , SDTIntBinOp, + [SDNPCommutative, SDNPAssociative]>; +def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; +def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; +def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; +def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; +def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; +def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; def and : SDNode<"ISD::AND" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def or : SDNode<"ISD::OR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; -def add : SDNode<"ISD::ADD" , SDTBinOp , - [SDNPCommutative, SDNPAssociative]>; -def sub : SDNode<"ISD::SUB" , SDTBinOp>; -def mul : SDNode<"ISD::MUL" , SDTBinOp , - [SDNPCommutative, SDNPAssociative]>; -def sdiv : SDNode<"ISD::SDIV" , SDTBinOp>; -def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; -def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; -def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; +def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; +def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; +def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; +def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; +def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; + def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;