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[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224991 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
2014-12-30 17:39:24 +00:00
parent af9e1c79a5
commit 066f43435a
3 changed files with 146 additions and 52 deletions
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4
test/MC/Disassembler/Hexagon/alu32_pred.txt
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@@ -60,6 +60,10 @@
# CHECK: p3 = cmp.gtu(r21, r31)
0x13 0xdf 0x75 0xf2
# CHECK: p3 = !cmp.gtu(r21, r31)
0xf1 0xe3 0x55 0x73
# CHECK: r17 = cmp.eq(r21, #31)
0xf1 0xe3 0x75 0x73
# CHECK: r17 = !cmp.eq(r21, #31)
0x11 0xdf 0x55 0xf3
# CHECK: r17 = cmp.eq(r21, r31)
0x11 0xdf 0x75 0xf3

24
test/MC/Disassembler/Hexagon/xtype_pred.txt
View File

@@ -1,5 +1,29 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
0x43 0xd5 0xd1 0xc7
# CHECK: p3 = cmpb.gt(r17, r21)
0xc3 0xd5 0xd1 0xc7
# CHECK: p3 = cmpb.eq(r17, r21)
0xe3 0xd5 0xd1 0xc7
# CHECK: p3 = cmpb.gtu(r17, r21)
0xa3 0xc2 0x11 0xdd
# CHECK: p3 = cmpb.eq(r17, #21)
0xa3 0xc2 0x31 0xdd
# CHECK: p3 = cmpb.gt(r17, #21)
0xa3 0xc2 0x51 0xdd
# CHECK: p3 = cmpb.gtu(r17, #21)
0x63 0xd5 0xd1 0xc7
# CHECK: p3 = cmph.eq(r17, r21)
0x83 0xd5 0xd1 0xc7
# CHECK: p3 = cmph.gt(r17, r21)
0xa3 0xd5 0xd1 0xc7
# CHECK: p3 = cmph.gtu(r17, r21)
0xab 0xc2 0x11 0xdd
# CHECK: p3 = cmph.eq(r17, #21)
0xab 0xc2 0x31 0xdd
# CHECK: p3 = cmph.gt(r17, #21)
0xab 0xc2 0x51 0xdd
# CHECK: p3 = cmph.gtu(r17, #21)
0x03 0xde 0x94 0xd2
# CHECK: p3 = cmp.eq(r21:20, r31:30)
0x43 0xde 0x94 0xd2