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Bug in ExpandFCOPYSIGNToBitwiseOps(). Clear the old sign bit of operand 0

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before or'ing in the sign bit of operand 1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-01-05 21:31:51 +00:00
parent 489a87ca09
commit 068c5f47ea
1 changed files with 14 additions and 4 deletions
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18
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -533,15 +533,17 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
static static
SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
SelectionDAG &DAG, TargetLowering &TLI) { SelectionDAG &DAG, TargetLowering &TLI) {
MVT::ValueType VT = Node->getValueType(0);
MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
// First get the sign bit of second operand. // First get the sign bit of second operand.
SDOperand Mask = (SrcVT == MVT::f64) SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask); Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask); SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
// Shift right or sign-extend it if the two operands have different types. // Shift right or sign-extend it if the two operands have different types.
int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
if (SizeDiff > 0) { if (SizeDiff > 0) {
@ -550,8 +552,16 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
} else if (SizeDiff < 0) } else if (SizeDiff < 0)
SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
// Or the first operand with the sign bit.
// Clear the sign bit of first operand.
SDOperand Mask2 = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
// Or the value with the sign bit.
Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
return Result; return Result;
} }