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tblgen: always lookup values from the original vector as it could be grown under our feet.
PR16281. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183630 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -890,9 +890,9 @@ void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
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/// Infer classes from per-processor InstReadWrite definitions.
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void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
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const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
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const RecVec *InstDefs = Sets.expand(*RWI);
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for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) {
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Record *Rec = SchedClasses[SCIdx].InstRWs[I];
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const RecVec *InstDefs = Sets.expand(Rec);
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RecIter II = InstDefs->begin(), IE = InstDefs->end();
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for (; II != IE; ++II) {
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if (InstrClassMap[*II] == SCIdx)
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@ -903,10 +903,10 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
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if (II == IE)
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continue;
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IdxVec Writes, Reads;
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findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
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unsigned PIdx = getProcModel((*RWI)->getValueAsDef("SchedModel")).Index;
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findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
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unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
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IdxVec ProcIndices(1, PIdx);
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inferFromRW(Writes, Reads, SCIdx, ProcIndices);
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inferFromRW(Writes, Reads, SCIdx, ProcIndices); // May mutate SchedClasses.
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}
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}
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