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https://github.com/c64scene-ar/llvm-6502.git
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Convert the PPC backend to use the new FMA infrastructure.
The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158955 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
cd88efe516
commit
070b8dba80
@ -132,12 +132,12 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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setOperationAction(ISD::FMA , MVT::f64, Expand);
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setOperationAction(ISD::FMA , MVT::f64, Legal);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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setOperationAction(ISD::FMA , MVT::f32, Expand);
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setOperationAction(ISD::FMA , MVT::f32, Legal);
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setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
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@ -378,6 +378,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
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setOperationAction(ISD::MUL, MVT::v4f32, Legal);
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setOperationAction(ISD::FMA, MVT::v4f32, Legal);
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setOperationAction(ISD::MUL, MVT::v4i32, Custom);
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setOperationAction(ISD::MUL, MVT::v8i16, Custom);
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setOperationAction(ISD::MUL, MVT::v16i8, Custom);
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@ -5876,6 +5877,26 @@ EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
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}
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}
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/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
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/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
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/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
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/// is expanded to mul + add.
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bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
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if (!VT.isSimple())
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return false;
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switch (VT.getSimpleVT().SimpleTy) {
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case MVT::f32:
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case MVT::f64:
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case MVT::v4f32:
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return true;
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default:
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break;
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}
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return false;
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}
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Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
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if (DisableILPPref)
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return TargetLowering::getSchedulingPreference(N);
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@ -366,6 +366,12 @@ namespace llvm {
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bool IsZeroVal, bool MemcpyStrSrc,
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MachineFunction &MF) const;
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/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
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/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
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/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
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/// is expanded to mul + add.
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virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
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private:
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SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
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SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
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@ -274,15 +274,11 @@ let PPC970_Unit = 5 in { // VALU Operations.
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vmaddfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB))]>,
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Requires<[FPContractions]>;
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[(set VRRC:$vD, (fma VRRC:$vA, VRRC:$vC, VRRC:$vB))]>;
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def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fsub V_immneg0,
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(fsub (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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[(set VRRC:$vD, (fneg (fma VRRC:$vA, VRRC:$vC,
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(fneg VRRC:$vB))))]>;
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def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
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def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
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@ -353,7 +353,6 @@ def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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def FPContractions : Predicate<"TM.Options.AllowExcessFPPrecision">;
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def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
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def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
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def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
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@ -1312,51 +1311,43 @@ let Uses = [RM] in {
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def FMADD : AForm_1<63, 29,
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(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
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"fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
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[(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
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F8RC:$FRB))]>,
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Requires<[FPContractions]>;
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[(set F8RC:$FRT,
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(fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>;
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def FMADDS : AForm_1<59, 29,
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(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
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"fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
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[(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
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F4RC:$FRB))]>,
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Requires<[FPContractions]>;
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[(set F4RC:$FRT,
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(fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>;
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def FMSUB : AForm_1<63, 28,
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(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
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"fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
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[(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
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F8RC:$FRB))]>,
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Requires<[FPContractions]>;
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[(set F8RC:$FRT,
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(fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>;
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def FMSUBS : AForm_1<59, 28,
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(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
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"fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
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[(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
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F4RC:$FRB))]>,
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Requires<[FPContractions]>;
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[(set F4RC:$FRT,
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(fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>;
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def FNMADD : AForm_1<63, 31,
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(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
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"fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
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[(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
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F8RC:$FRB)))]>,
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Requires<[FPContractions]>;
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[(set F8RC:$FRT,
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(fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>;
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def FNMADDS : AForm_1<59, 31,
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(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
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"fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
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[(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
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F4RC:$FRB)))]>,
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Requires<[FPContractions]>;
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[(set F4RC:$FRT,
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(fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>;
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def FNMSUB : AForm_1<63, 30,
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(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
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"fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
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[(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
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F8RC:$FRB)))]>,
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Requires<[FPContractions]>;
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[(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC,
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(fneg F8RC:$FRB))))]>;
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def FNMSUBS : AForm_1<59, 30,
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(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
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"fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
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[(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
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F4RC:$FRB)))]>,
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Requires<[FPContractions]>;
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[(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC,
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(fneg F4RC:$FRB))))]>;
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}
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// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
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// having 4 of these, force the comparison to always be an 8-byte double (code
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@ -1517,14 +1508,6 @@ def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
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def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
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(ADDIS GPRC:$in, tblockaddress:$g)>;
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// Fused negative multiply subtract, alternate pattern
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def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
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(FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
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Requires<[FPContractions]>;
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def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
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(FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
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Requires<[FPContractions]>;
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// Standard shifts. These are represented separately from the real shifts above
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// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
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// amounts.
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