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https://github.com/c64scene-ar/llvm-6502.git
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* Start renaming MachineInstrInfo -> TargetInstrInfo
* Add new M_TERMINATOR_FLAG git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5213 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
09d4fd57de
commit
075b4a066d
@ -1,4 +1,4 @@
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//===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===//
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//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// This file describes the target machine instructions to the code generator.
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//
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@ -10,7 +10,6 @@
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#include "Support/DataTypes.h"
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#include <vector>
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class MachineInstrDescriptor;
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class MachineInstr;
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class TargetMachine;
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class Value;
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@ -39,25 +38,31 @@ const MachineOpCode INVALID_MACHINE_OPCODE = -1;
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//
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//---------------------------------------------------------------------------
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const unsigned M_NOP_FLAG = 1 << 0;
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const unsigned M_BRANCH_FLAG = 1 << 1;
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const unsigned M_CALL_FLAG = 1 << 2;
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const unsigned M_RET_FLAG = 1 << 3;
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const unsigned M_ARITH_FLAG = 1 << 4;
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const unsigned M_CC_FLAG = 1 << 6;
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const unsigned M_LOGICAL_FLAG = 1 << 6;
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const unsigned M_INT_FLAG = 1 << 7;
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const unsigned M_FLOAT_FLAG = 1 << 8;
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const unsigned M_CONDL_FLAG = 1 << 9;
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const unsigned M_LOAD_FLAG = 1 << 10;
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const unsigned M_PREFETCH_FLAG = 1 << 11;
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const unsigned M_STORE_FLAG = 1 << 12;
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const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
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const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
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const unsigned M_NOP_FLAG = 1 << 0;
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const unsigned M_BRANCH_FLAG = 1 << 1;
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const unsigned M_CALL_FLAG = 1 << 2;
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const unsigned M_RET_FLAG = 1 << 3;
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const unsigned M_ARITH_FLAG = 1 << 4;
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const unsigned M_CC_FLAG = 1 << 6;
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const unsigned M_LOGICAL_FLAG = 1 << 6;
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const unsigned M_INT_FLAG = 1 << 7;
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const unsigned M_FLOAT_FLAG = 1 << 8;
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const unsigned M_CONDL_FLAG = 1 << 9;
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const unsigned M_LOAD_FLAG = 1 << 10;
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const unsigned M_PREFETCH_FLAG = 1 << 11;
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const unsigned M_STORE_FLAG = 1 << 12;
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const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
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const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
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// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
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const unsigned M_2_ADDR_FLAG = 1 << 15;
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const unsigned M_2_ADDR_FLAG = 1 << 15;
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struct MachineInstrDescriptor {
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// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
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// block? Typically this is things like return and branch instructions.
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// Various passes use this to insert code into the bottom of a basic block, but
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// before control flow occurs.
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const unsigned M_TERMINATOR_FLAG = 1 << 16;
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struct TargetInstrDescriptor {
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const char * Name; // Assembly language mnemonic for the opcode.
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int numOperands; // Number of args; -1 if variable #args
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int resultPos; // Position of the result; -1 if no result
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@ -73,18 +78,19 @@ struct MachineInstrDescriptor {
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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};
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typedef TargetInstrDescriptor MachineInstrDescriptor;
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class MachineInstrInfo {
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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class TargetInstrInfo {
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const TargetInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~MachineInstrInfo();
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TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~TargetInstrInfo();
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// Invariant: All instruction sets use opcode #0 as the PHI instruction and
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// opcode #1 as the noop instruction.
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@ -98,7 +104,7 @@ public:
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const MachineInstrDescriptor& get(MachineOpCode opCode) const {
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const TargetInstrDescriptor& get(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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@ -187,15 +193,18 @@ public:
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|| get(opCode).Flags & M_PREFETCH_FLAG
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|| get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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bool isDummyPhiInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(const MachineOpCode opCode) const {
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bool isPseudoInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_PSEUDO_FLAG;
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}
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bool isTwoAddrInstr(const MachineOpCode opCode) const {
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bool isTwoAddrInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_2_ADDR_FLAG;
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}
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bool isTerminatorInstr(unsigned Opcode) const {
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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@ -372,4 +381,6 @@ public:
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}
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};
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typedef TargetInstrInfo MachineInstrInfo;
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#endif
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@ -1,4 +1,4 @@
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//===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===//
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//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// This file describes the target machine instructions to the code generator.
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//
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@ -10,7 +10,6 @@
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#include "Support/DataTypes.h"
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#include <vector>
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class MachineInstrDescriptor;
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class MachineInstr;
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class TargetMachine;
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class Value;
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@ -39,25 +38,31 @@ const MachineOpCode INVALID_MACHINE_OPCODE = -1;
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//
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//---------------------------------------------------------------------------
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const unsigned M_NOP_FLAG = 1 << 0;
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const unsigned M_BRANCH_FLAG = 1 << 1;
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const unsigned M_CALL_FLAG = 1 << 2;
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const unsigned M_RET_FLAG = 1 << 3;
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const unsigned M_ARITH_FLAG = 1 << 4;
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const unsigned M_CC_FLAG = 1 << 6;
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const unsigned M_LOGICAL_FLAG = 1 << 6;
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const unsigned M_INT_FLAG = 1 << 7;
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const unsigned M_FLOAT_FLAG = 1 << 8;
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const unsigned M_CONDL_FLAG = 1 << 9;
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const unsigned M_LOAD_FLAG = 1 << 10;
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const unsigned M_PREFETCH_FLAG = 1 << 11;
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const unsigned M_STORE_FLAG = 1 << 12;
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const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
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const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
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const unsigned M_NOP_FLAG = 1 << 0;
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const unsigned M_BRANCH_FLAG = 1 << 1;
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const unsigned M_CALL_FLAG = 1 << 2;
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const unsigned M_RET_FLAG = 1 << 3;
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const unsigned M_ARITH_FLAG = 1 << 4;
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const unsigned M_CC_FLAG = 1 << 6;
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const unsigned M_LOGICAL_FLAG = 1 << 6;
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const unsigned M_INT_FLAG = 1 << 7;
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const unsigned M_FLOAT_FLAG = 1 << 8;
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const unsigned M_CONDL_FLAG = 1 << 9;
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const unsigned M_LOAD_FLAG = 1 << 10;
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const unsigned M_PREFETCH_FLAG = 1 << 11;
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const unsigned M_STORE_FLAG = 1 << 12;
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const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
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const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
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// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
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const unsigned M_2_ADDR_FLAG = 1 << 15;
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const unsigned M_2_ADDR_FLAG = 1 << 15;
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struct MachineInstrDescriptor {
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// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
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// block? Typically this is things like return and branch instructions.
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// Various passes use this to insert code into the bottom of a basic block, but
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// before control flow occurs.
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const unsigned M_TERMINATOR_FLAG = 1 << 16;
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struct TargetInstrDescriptor {
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const char * Name; // Assembly language mnemonic for the opcode.
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int numOperands; // Number of args; -1 if variable #args
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int resultPos; // Position of the result; -1 if no result
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@ -73,18 +78,19 @@ struct MachineInstrDescriptor {
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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};
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typedef TargetInstrDescriptor MachineInstrDescriptor;
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class MachineInstrInfo {
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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class TargetInstrInfo {
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const TargetInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~MachineInstrInfo();
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TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~TargetInstrInfo();
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// Invariant: All instruction sets use opcode #0 as the PHI instruction and
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// opcode #1 as the noop instruction.
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@ -98,7 +104,7 @@ public:
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const MachineInstrDescriptor& get(MachineOpCode opCode) const {
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const TargetInstrDescriptor& get(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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@ -187,15 +193,18 @@ public:
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|| get(opCode).Flags & M_PREFETCH_FLAG
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|| get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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bool isDummyPhiInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(const MachineOpCode opCode) const {
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bool isPseudoInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_PSEUDO_FLAG;
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}
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bool isTwoAddrInstr(const MachineOpCode opCode) const {
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bool isTwoAddrInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_2_ADDR_FLAG;
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}
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bool isTerminatorInstr(unsigned Opcode) const {
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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@ -372,4 +381,6 @@ public:
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}
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};
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typedef TargetInstrInfo MachineInstrInfo;
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#endif
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