6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-30 17:33:24 +00:00
Code Issues Projects Releases Wiki Activity

Thumb parsing and encoding support for NOP.

Browse Source 
The irony is not lost that this is not a completely trivial patchset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-19 23:24:36 +00:00
parent cc29861901
commit 0780b6303b
5 changed files with 24 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/ARM/ARMInstrThumb.td
View File

@ -237,7 +237,8 @@ class T1SystemEncoding<bits<8> opc>
}
def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
T1SystemEncoding<0x00>; // A8.6.110
T1SystemEncoding<0x00>, // A8.6.110
Requires<[IsThumb2]>;
def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
T1SystemEncoding<0x10>; // A8.6.410
@ -1382,3 +1383,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2, IIC_Br, [(brind GPR:$Rm)],
(tMOVr PC, GPR:$Rm, pred:$p)>;
}
// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
// encoding is available on ARMv6K, but we don't differentiate that finely.
def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;

1
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -2846,6 +2846,7 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
Mnemonic == "setend" ||
(Mnemonic == "nop" && isThumbOne()) ||
((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
&& !isThumb()) ||

7
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -169,6 +169,13 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
return;
}
// Thumb1 NOP
if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
return;
}
printInstruction(MI, O);
}

8
test/MC/ARM/basic-thumb-instructions.s
View File

@ -347,3 +347,11 @@ _func:
negs r3, r4
@ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42]
@------------------------------------------------------------------------------
@ NOP
@------------------------------------------------------------------------------
nop
@ CHECK: nop @ encoding: [0xc0,0x46]

2
test/MC/ARM/thumb.s
View File

@ -42,7 +42,7 @@
@ CHECK: bkpt #2 @ encoding: [0x02,0xbe]
nop
@ CHECK: nop @ encoding: [0x00,0xbf]
@ CHECK: nop @ encoding: [0xc0,0x46]
wfe
wfi