6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 21:32:39 +00:00
Code Issues Projects Releases Wiki Activity

Make code a little less verbose.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-01-22 03:07:48 +00:00
parent 69c96d71dd
commit 07a276277f
1 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/X86/X86ISelLowering.cpp
View File

@ -5052,11 +5052,10 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (ISD::isBuildVectorAllZeros(Op.getNode())) { if (ISD::isBuildVectorAllZeros(Op.getNode())) {
// Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
// and 2) ensure that i64 scalars are eliminated on x86-32 hosts. // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
if (Op.getValueType() == MVT::v4i32 || if (VT == MVT::v4i32 || VT == MVT::v8i32)
Op.getValueType() == MVT::v8i32)
return Op; return Op;
return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), return getZeroVector(VT, Subtarget->hasSSE2(),
Subtarget->hasAVX2(), DAG, dl); Subtarget->hasAVX2(), DAG, dl);
} }
@ -5064,11 +5063,10 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
// vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
// vpcmpeqd on 256-bit vectors. // vpcmpeqd on 256-bit vectors.
if (ISD::isBuildVectorAllOnes(Op.getNode())) { if (ISD::isBuildVectorAllOnes(Op.getNode())) {
if (Op.getValueType() == MVT::v4i32 || if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
(Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
return Op; return Op;
return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl); return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
} }
SDValue LD = isVectorBroadcast(Op, Subtarget); SDValue LD = isVectorBroadcast(Op, Subtarget);
@ -5137,7 +5135,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
DAG.getUNDEF(Item.getValueType()), DAG.getUNDEF(Item.getValueType()),
&Mask[0]); &Mask[0]);
} }
return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); return DAG.getNode(ISD::BITCAST, dl, VT, Item);
} }
} }