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ARM: rGPR is meant to be unpredictable, not undefined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184706 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -916,8 +916,11 @@ static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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uint64_t Address, const void *Decoder) {
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if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
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DecodeStatus S = MCDisassembler::Success;
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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if (RegNo == 13 || RegNo == 15)
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S = MCDisassembler::SoftFail;
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Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
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return S;
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}
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}
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static const uint16_t SPRDecoderTable[] = {
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static const uint16_t SPRDecoderTable[] = {
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined"
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# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
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# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -1,5 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined"
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# XFAIL: *
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# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
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# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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