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[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
69ae8f1abd
commit
0821c72f11
@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td)
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tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter)
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tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
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@ -14,7 +14,8 @@ TARGET = Sparc
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
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SparcGenAsmWriter.inc SparcGenDAGISel.inc \
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SparcGenSubtargetInfo.inc SparcGenCallingConv.inc
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SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
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SparcGenCodeEmitter.inc
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DIRS = TargetInfo MCTargetDesc
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@ -111,6 +111,32 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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let Inst{4-0} = rs2;
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}
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// floating-point unary operations.
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class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let rs1 = 0;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// floating-point compares.
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class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let rd = 0;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// Shift by register rs2.
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class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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@ -259,8 +259,9 @@ let hasSideEffects = 1, mayStore = 1 in {
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[(flushw)]>;
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}
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def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
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"unimp $val", []>;
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let rd = 0 in
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def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
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"unimp $val", []>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence. This has to handle all
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@ -511,9 +512,10 @@ defm SUB : F3_12 <"sub" , 0b000100, sub>;
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let Uses = [ICC] in
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defm SUBX : F3_12 <"subx" , 0b001100, sube>;
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let Defs = [ICC] in {
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let Defs = [ICC] in
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defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
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let Defs = [ICC], rd = 0 in {
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def CMPrr : F3_1<2, 0b010100,
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(outs), (ins IntRegs:$b, IntRegs:$c),
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"cmp $b, $c",
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@ -571,7 +573,7 @@ class BranchSP<dag ins, string asmstr, list<dag> pattern>
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// Indirect branch instructions.
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let isTerminator = 1, isBarrier = 1,
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hasDelaySlot = 1, isBranch =1,
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isIndirectBranch = 1 in {
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isIndirectBranch = 1, rd = 0 in {
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def BINDrr : F3_1<2, 0b111000,
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(outs), (ins MEMrr:$ptr),
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"jmp $ptr",
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@ -618,21 +620,21 @@ let Uses = [O6],
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def JMPLrr : F3_1<2, 0b111000,
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(outs), (ins MEMrr:$ptr, variable_ops),
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"call $ptr",
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[(call ADDRrr:$ptr)]>;
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[(call ADDRrr:$ptr)]> { let rd = 15; }
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def JMPLri : F3_2<2, 0b111000,
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(outs), (ins MEMri:$ptr, variable_ops),
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"call $ptr",
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[(call ADDRri:$ptr)]>;
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[(call ADDRri:$ptr)]> { let rd = 15; }
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}
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// Section B.28 - Read State Register Instructions
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let Uses = [Y] in
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let Uses = [Y], rs1 = 0, rs2 = 0 in
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def RDY : F3_1<2, 0b101000,
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(outs IntRegs:$dst), (ins),
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"rd %y, $dst", []>;
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// Section B.29 - Write State Register Instructions
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let Defs = [Y] in {
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let Defs = [Y], rd = 0 in {
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def WRYrr : F3_1<2, 0b110000,
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(outs), (ins IntRegs:$b, IntRegs:$c),
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"wr $b, $c, %y", []>;
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@ -641,89 +643,89 @@ let Defs = [Y] in {
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"wr $b, $c, %y", []>;
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}
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3<2, 0b110100, 0b011000100,
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def FITOS : F3_3u<2, 0b110100, 0b011000100,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fitos $src, $dst",
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[(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
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def FITOD : F3_3<2, 0b110100, 0b011001000,
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def FITOD : F3_3u<2, 0b110100, 0b011001000,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fitod $src, $dst",
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[(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
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def FITOQ : F3_3<2, 0b110100, 0b011001100,
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def FITOQ : F3_3u<2, 0b110100, 0b011001100,
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(outs QFPRegs:$dst), (ins FPRegs:$src),
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"fitoq $src, $dst",
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[(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
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Requires<[HasHardQuad]>;
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// Convert Floating-point to Integer Instructions, p. 142
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def FSTOI : F3_3<2, 0b110100, 0b011010001,
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def FSTOI : F3_3u<2, 0b110100, 0b011010001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fstoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
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def FDTOI : F3_3<2, 0b110100, 0b011010010,
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def FDTOI : F3_3u<2, 0b110100, 0b011010010,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
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def FQTOI : F3_3<2, 0b110100, 0b011010011,
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def FQTOI : F3_3u<2, 0b110100, 0b011010011,
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(outs FPRegs:$dst), (ins QFPRegs:$src),
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"fqtoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
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Requires<[HasHardQuad]>;
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3<2, 0b110100, 0b011001001,
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def FSTOD : F3_3u<2, 0b110100, 0b011001001,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fstod $src, $dst",
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[(set f64:$dst, (fextend f32:$src))]>;
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def FSTOQ : F3_3<2, 0b110100, 0b011001101,
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def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
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(outs QFPRegs:$dst), (ins FPRegs:$src),
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"fstoq $src, $dst",
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[(set f128:$dst, (fextend f32:$src))]>,
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Requires<[HasHardQuad]>;
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def FDTOS : F3_3<2, 0b110100, 0b011000110,
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def FDTOS : F3_3u<2, 0b110100, 0b011000110,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtos $src, $dst",
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[(set f32:$dst, (fround f64:$src))]>;
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def FDTOQ : F3_3<2, 0b110100, 0b01101110,
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def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
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(outs QFPRegs:$dst), (ins DFPRegs:$src),
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"fdtoq $src, $dst",
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[(set f128:$dst, (fextend f64:$src))]>,
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Requires<[HasHardQuad]>;
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def FQTOS : F3_3<2, 0b110100, 0b011000111,
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def FQTOS : F3_3u<2, 0b110100, 0b011000111,
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(outs FPRegs:$dst), (ins QFPRegs:$src),
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"fqtos $src, $dst",
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[(set f32:$dst, (fround f128:$src))]>,
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Requires<[HasHardQuad]>;
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def FQTOD : F3_3<2, 0b110100, 0b011001011,
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def FQTOD : F3_3u<2, 0b110100, 0b011001011,
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(outs DFPRegs:$dst), (ins QFPRegs:$src),
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"fqtod $src, $dst",
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[(set f64:$dst, (fround f128:$src))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3<2, 0b110100, 0b000000001,
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def FMOVS : F3_3u<2, 0b110100, 0b000000001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fmovs $src, $dst", []>;
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def FNEGS : F3_3<2, 0b110100, 0b000000101,
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def FNEGS : F3_3u<2, 0b110100, 0b000000101,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fnegs $src, $dst",
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[(set f32:$dst, (fneg f32:$src))]>;
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def FABSS : F3_3<2, 0b110100, 0b000001001,
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def FABSS : F3_3u<2, 0b110100, 0b000001001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fabss $src, $dst",
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[(set f32:$dst, (fabs f32:$src))]>;
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// Floating-point Square Root Instructions, p.145
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def FSQRTS : F3_3<2, 0b110100, 0b000101001,
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def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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"fsqrts $src, $dst",
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[(set f32:$dst, (fsqrt f32:$src))]>;
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def FSQRTD : F3_3<2, 0b110100, 0b000101010,
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def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fsqrtd $src, $dst",
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[(set f64:$dst, (fsqrt f64:$src))]>;
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def FSQRTQ : F3_3<2, 0b110100, 0b000101011,
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def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fsqrtq $src, $dst",
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[(set f128:$dst, (fsqrt f128:$src))]>,
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@ -808,15 +810,15 @@ def FDIVQ : F3_3<2, 0b110100, 0b001001111,
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// after the instr is retired, but there is no interlock. This behavior
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// is modelled with a forced noop after the instruction.
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let Defs = [FCC] in {
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def FCMPS : F3_3<2, 0b110101, 0b001010001,
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def FCMPS : F3_3c<2, 0b110101, 0b001010001,
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(outs), (ins FPRegs:$src1, FPRegs:$src2),
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"fcmps $src1, $src2\n\tnop",
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[(SPcmpfcc f32:$src1, f32:$src2)]>;
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def FCMPD : F3_3<2, 0b110101, 0b001010010,
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def FCMPD : F3_3c<2, 0b110101, 0b001010010,
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(outs), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fcmpd $src1, $src2\n\tnop",
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[(SPcmpfcc f64:$src1, f64:$src2)]>;
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def FCMPQ : F3_3<2, 0b110101, 0b001010011,
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def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
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(outs), (ins QFPRegs:$src1, QFPRegs:$src2),
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"fcmpq $src1, $src2\n\tnop",
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[(SPcmpfcc f128:$src1, f128:$src2)]>,
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@ -927,27 +929,27 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in {
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// Floating-Point Move Instructions, p. 164 of the V9 manual.
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let Predicates = [HasV9] in {
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def FMOVD : F3_3<2, 0b110100, 0b000000010,
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def FMOVD : F3_3u<2, 0b110100, 0b000000010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fmovd $src, $dst", []>;
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def FMOVQ : F3_3<2, 0b110100, 0b000000011,
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def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fmovq $src, $dst", []>,
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Requires<[HasHardQuad]>;
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def FNEGD : F3_3<2, 0b110100, 0b000000110,
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def FNEGD : F3_3u<2, 0b110100, 0b000000110,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fnegd $src, $dst",
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[(set f64:$dst, (fneg f64:$src))]>;
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def FNEGQ : F3_3<2, 0b110100, 0b000000111,
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def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fnegq $src, $dst",
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[(set f128:$dst, (fneg f128:$src))]>,
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Requires<[HasHardQuad]>;
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def FABSD : F3_3<2, 0b110100, 0b000001010,
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def FABSD : F3_3u<2, 0b110100, 0b000001010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fabsd $src, $dst",
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[(set f64:$dst, (fabs f64:$src))]>;
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def FABSQ : F3_3<2, 0b110100, 0b000001011,
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def FABSQ : F3_3u<2, 0b110100, 0b000001011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fabsq $src, $dst",
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[(set f128:$dst, (fabs f128:$src))]>,
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@ -956,9 +958,10 @@ let Predicates = [HasV9] in {
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// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
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// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
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def POPCrr : F3_1<2, 0b101110,
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(outs IntRegs:$dst), (ins IntRegs:$src),
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"popc $src, $dst", []>, Requires<[HasV9]>;
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let rs1 = 0 in
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def POPCrr : F3_1<2, 0b101110,
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(outs IntRegs:$dst), (ins IntRegs:$src),
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"popc $src, $dst", []>, Requires<[HasV9]>;
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def : Pat<(ctpop i32:$src),
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(POPCrr (SLLri $src, 0))>;
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