mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 06:33:24 +00:00
Revise td of X86 atomic instructions
- Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164357 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
258aeb5762
commit
0838249a6a
@ -12153,6 +12153,11 @@ X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
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BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
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break;
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}
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case X86::ATOMMAX8:
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case X86::ATOMMIN8:
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case X86::ATOMUMAX8:
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case X86::ATOMUMIN8:
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llvm_unreachable("Not supported yet!");
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case X86::ATOMMAX16:
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case X86::ATOMMAX32:
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case X86::ATOMMAX64:
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@ -482,124 +482,73 @@ def CMOV_RFP80 : I<0, Pseudo,
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// Atomic Instruction Pseudo Instructions
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//===----------------------------------------------------------------------===//
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// Pseudo atomic instructions
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multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
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let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
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def #NAME#8 : I<0, Pseudo, (outs GR8:$dst),
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(ins i8mem:$ptr, GR8:$val),
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!strconcat(mnemonic, "8 PSEUDO!"), []>;
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def #NAME#16 : I<0, Pseudo,(outs GR16:$dst),
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(ins i16mem:$ptr, GR16:$val),
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!strconcat(mnemonic, "16 PSEUDO!"), []>;
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def #NAME#32 : I<0, Pseudo, (outs GR32:$dst),
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(ins i32mem:$ptr, GR32:$val),
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!strconcat(mnemonic, "32 PSEUDO!"), []>;
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def #NAME#64 : I<0, Pseudo, (outs GR64:$dst),
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(ins i64mem:$ptr, GR64:$val),
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!strconcat(mnemonic, "64 PSEUDO!"), []>;
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}
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}
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multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
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def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
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(!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
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def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
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(!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
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def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
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(!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
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def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
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(!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
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}
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// Atomic exchange, and, or, xor
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let usesCustomInserter = 1 in {
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defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
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defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
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defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
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defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
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defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
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defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
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defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
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defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
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def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMAND8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
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def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMOR8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
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def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMXOR8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
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def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
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"#ATOMNAND8 PSEUDO!",
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[(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
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defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
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def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMAND16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
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def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMOR16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
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def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMXOR16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
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def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMNAND16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
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def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
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"#ATOMMIN16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
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def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMMAX16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
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def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMUMIN16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
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def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
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"#ATOMUMAX16 PSEUDO!",
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[(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
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def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMAND32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
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def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMOR32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
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def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMXOR32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
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def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMNAND32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
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def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
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"#ATOMMIN32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
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def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMMAX32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
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def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMUMIN32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
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def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMUMAX32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
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def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMAND64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
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def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMOR64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
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def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMXOR64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
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def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMNAND64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
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def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
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"#ATOMMIN64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
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def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMMAX64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
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def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMUMIN64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
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def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMUMAX64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
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multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
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let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in
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def #NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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!strconcat(mnemonic, "6432 PSEUDO!"), []>;
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}
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let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in {
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def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMAND6432 PSEUDO!", []>;
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def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMOR6432 PSEUDO!", []>;
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def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMXOR6432 PSEUDO!", []>;
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def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMNAND6432 PSEUDO!", []>;
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def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMADD6432 PSEUDO!", []>;
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def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMSUB6432 PSEUDO!", []>;
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def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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"#ATOMSWAP6432 PSEUDO!", []>;
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}
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defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMAND">;
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defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMOR">;
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defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMXOR">;
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defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMNAND">;
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defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMADD">;
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defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMSUB">;
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defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMMAX">;
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defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMMIN">;
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defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMUMAX">;
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defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMUMIN">;
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defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMSWAP">;
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//===----------------------------------------------------------------------===//
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// Normal-Instructions-With-Lock-Prefix Pseudo Instructions
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@ -712,107 +661,125 @@ defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
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defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
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// Optimized codegen when the non-memory output is not used.
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multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
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string mnemonic> {
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let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
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def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
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"lock\n\t"
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"inc{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
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"lock\n\t"
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"inc{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
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def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
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"lock\n\t"
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"inc{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
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"lock\n\t"
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"inc{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
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"lock\n\t"
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"dec{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
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"lock\n\t"
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"dec{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
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def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
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"lock\n\t"
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"dec{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
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"lock\n\t"
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"dec{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def #NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
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!strconcat("lock\n\t", mnemonic, "{b}\t$dst"),
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[], IIC_UNARY_MEM>, LOCK;
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def #NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
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!strconcat("lock\n\t", mnemonic, "{w}\t$dst"),
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[], IIC_UNARY_MEM>, OpSize, LOCK;
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def #NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
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!strconcat("lock\n\t", mnemonic, "{l}\t$dst"),
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[], IIC_UNARY_MEM>, LOCK;
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def #NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
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!strconcat("lock\n\t", mnemonic, "{q}\t$dst"),
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[], IIC_UNARY_MEM>, LOCK;
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}
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}
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defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
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defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
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// Atomic compare and swap.
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let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
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isCodeGenOnly = 1 in
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def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
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"lock\n\t"
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"cmpxchg8b\t$ptr",
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[(X86cas8 addr:$ptr)], IIC_CMPX_LOCK_8B>, TB, LOCK;
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multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
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SDPatternOperator frag, X86MemOperand x86memop,
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InstrItinClass itin> {
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let isCodeGenOnly = 1 in {
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def #NAME# : I<Opc, Form, (outs), (ins x86memop:$ptr),
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!strconcat("lock\n\t", mnemonic, "\t$ptr"),
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[(frag addr:$ptr)], itin>, TB, LOCK;
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}
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}
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multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
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string mnemonic, SDPatternOperator frag,
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InstrItinClass itin8, InstrItinClass itin> {
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let isCodeGenOnly = 1 in {
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let Defs = [AL, EFLAGS], Uses = [AL] in
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def #NAME#8 : I<Opc, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
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!strconcat("lock\n\t", mnemonic,
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"{b}\t{$swap, $ptr|$ptr, $swap}"),
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[(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
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let Defs = [AX, EFLAGS], Uses = [AX] in
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def #NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
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!strconcat("lock\n\t", mnemonic,
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"{w}\t{$swap, $ptr|$ptr, $swap}"),
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[(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
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let Defs = [EAX, EFLAGS], Uses = [EAX] in
|
||||
def #NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
|
||||
!strconcat("lock\n\t", mnemonic,
|
||||
"{l}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
|
||||
let Defs = [RAX, EFLAGS], Uses = [RAX] in
|
||||
def #NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
|
||||
!strconcat("lock\n\t", mnemonic,
|
||||
"{q}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
|
||||
}
|
||||
}
|
||||
|
||||
let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
|
||||
defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
|
||||
X86cas8, i64mem,
|
||||
IIC_CMPX_LOCK_8B>;
|
||||
}
|
||||
|
||||
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
|
||||
isCodeGenOnly = 1 in
|
||||
def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
|
||||
"lock\n\t"
|
||||
"cmpxchg16b\t$ptr",
|
||||
[(X86cas16 addr:$ptr)], IIC_CMPX_LOCK_16B>, TB, LOCK,
|
||||
Requires<[HasCmpxchg16b]>;
|
||||
|
||||
let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
|
||||
def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
|
||||
"lock\n\t"
|
||||
"cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
|
||||
[(X86cas addr:$ptr, GR8:$swap, 1)], IIC_CMPX_LOCK_8>, TB, LOCK;
|
||||
Predicates = [HasCmpxchg16b] in {
|
||||
defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
|
||||
X86cas16, i128mem,
|
||||
IIC_CMPX_LOCK_16B>, REX_W;
|
||||
}
|
||||
|
||||
let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
|
||||
def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
|
||||
"lock\n\t"
|
||||
"cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
|
||||
[(X86cas addr:$ptr, GR16:$swap, 2)], IIC_CMPX_LOCK>, TB, OpSize, LOCK;
|
||||
}
|
||||
|
||||
let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
|
||||
def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
|
||||
"lock\n\t"
|
||||
"cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
|
||||
[(X86cas addr:$ptr, GR32:$swap, 4)], IIC_CMPX_LOCK>, TB, LOCK;
|
||||
}
|
||||
|
||||
let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
|
||||
def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
|
||||
"lock\n\t"
|
||||
"cmpxchg{q}\t{$swap, $ptr|$ptr, $swap}",
|
||||
[(X86cas addr:$ptr, GR64:$swap, 8)], IIC_CMPX_LOCK>, TB, LOCK;
|
||||
}
|
||||
defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
|
||||
X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
|
||||
|
||||
// Atomic exchange and add
|
||||
let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
|
||||
def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{b}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))],
|
||||
IIC_XADD_LOCK_MEM8>,
|
||||
TB, LOCK;
|
||||
def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{w}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))],
|
||||
IIC_XADD_LOCK_MEM>,
|
||||
TB, OpSize, LOCK;
|
||||
def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{l}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))],
|
||||
IIC_XADD_LOCK_MEM>,
|
||||
TB, LOCK;
|
||||
def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{q}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))],
|
||||
IIC_XADD_LOCK_MEM>,
|
||||
TB, LOCK;
|
||||
multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
|
||||
string frag,
|
||||
InstrItinClass itin8, InstrItinClass itin> {
|
||||
let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
|
||||
def #NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
|
||||
(ins GR8:$val, i8mem:$ptr),
|
||||
!strconcat("lock\n\t", mnemonic,
|
||||
"{b}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set GR8:$dst,
|
||||
(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
|
||||
itin8>;
|
||||
def #NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
|
||||
(ins GR16:$val, i16mem:$ptr),
|
||||
!strconcat("lock\n\t", mnemonic,
|
||||
"{w}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR16:$dst,
|
||||
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
|
||||
itin>;
|
||||
def #NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$val, i32mem:$ptr),
|
||||
!strconcat("lock\n\t", mnemonic,
|
||||
"{l}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR32:$dst,
|
||||
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
|
||||
itin>;
|
||||
def #NAME#64 : I<opc, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$val, i64mem:$ptr),
|
||||
!strconcat("lock\n\t", mnemonic,
|
||||
"{q}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR64:$dst,
|
||||
(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
|
||||
itin>;
|
||||
}
|
||||
}
|
||||
|
||||
defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
|
||||
IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
|
||||
TB, LOCK;
|
||||
|
||||
def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
|
||||
"#ACQUIRE_MOV PSEUDO!",
|
||||
[(set GR8:$dst, (atomic_load_8 addr:$src))]>;
|
||||
|
||||
@ -1266,28 +1266,46 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
// Atomic support
|
||||
//
|
||||
|
||||
|
||||
// Atomic swap. These are just normal xchg instructions. But since a memory
|
||||
// operand is referenced, the atomicity is ensured.
|
||||
let Constraints = "$val = $dst" in {
|
||||
def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
||||
"xchg{b}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))],
|
||||
IIC_XCHG_MEM>;
|
||||
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
|
||||
"xchg{w}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))],
|
||||
IIC_XCHG_MEM>,
|
||||
OpSize;
|
||||
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
|
||||
"xchg{l}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))],
|
||||
IIC_XCHG_MEM>;
|
||||
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
|
||||
"xchg{q}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))],
|
||||
IIC_XCHG_MEM>;
|
||||
multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
|
||||
InstrItinClass itin> {
|
||||
let Constraints = "$val = $dst" in {
|
||||
def #NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
|
||||
(ins GR8:$val, i8mem:$ptr),
|
||||
!strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR8:$dst,
|
||||
(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
|
||||
itin>;
|
||||
def #NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
|
||||
(ins GR16:$val, i16mem:$ptr),
|
||||
!strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR16:$dst,
|
||||
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
|
||||
itin>, OpSize;
|
||||
def #NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$val, i32mem:$ptr),
|
||||
!strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR32:$dst,
|
||||
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
|
||||
itin>;
|
||||
def #NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$val, i64mem:$ptr),
|
||||
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR64:$dst,
|
||||
(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
|
||||
itin>;
|
||||
}
|
||||
}
|
||||
|
||||
defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
|
||||
|
||||
// Swap between registers.
|
||||
let Constraints = "$val = $dst" in {
|
||||
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
|
||||
"xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
|
||||
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
|
||||
@ -1298,6 +1316,7 @@ def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
|
||||
"xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
|
||||
}
|
||||
|
||||
// Swap between EAX and other registers.
|
||||
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
|
||||
"xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
|
||||
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user