From 0855dee564f80160abf95497475306af38ab7f84 Mon Sep 17 00:00:00 2001 From: David Goodwin Date: Tue, 10 Nov 2009 00:15:47 +0000 Subject: [PATCH] Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetSubtarget.h | 9 +++++++-- lib/CodeGen/AggressiveAntiDepBreaker.cpp | 14 +++++++++++++- lib/CodeGen/AggressiveAntiDepBreaker.h | 6 ++++-- lib/CodeGen/PostRASchedulerList.cpp | 5 +++-- lib/Target/ARM/ARMSubtarget.h | 8 ++++++-- lib/Target/X86/X86Subtarget.h | 6 ++++-- 6 files changed, 37 insertions(+), 11 deletions(-) diff --git a/include/llvm/Target/TargetSubtarget.h b/include/llvm/Target/TargetSubtarget.h index fd107e074cb..64c36d5f765 100644 --- a/include/llvm/Target/TargetSubtarget.h +++ b/include/llvm/Target/TargetSubtarget.h @@ -15,6 +15,8 @@ #define LLVM_TARGET_TARGETSUBTARGET_H #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/ADT/SmallVector.h" namespace llvm { @@ -36,6 +38,7 @@ public: // AntiDepBreakMode - Type of anti-dependence breaking that should // be performed before post-RA scheduling. typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; + typedef SmallVector ExcludedRCVector; virtual ~TargetSubtarget(); @@ -49,8 +52,10 @@ public: // scheduling and the specified optimization level meets the requirement // return true to enable post-register-allocation scheduling. virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - AntiDepBreakMode& mode) const { - mode = ANTIDEP_NONE; + AntiDepBreakMode& Mode, + ExcludedRCVector& ExcludedRCs) const { + Mode = ANTIDEP_NONE; + ExcludedRCs.clear(); return false; } diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index c10900c18d6..17b50bd9559 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -99,12 +99,24 @@ bool AggressiveAntiDepState::IsLive(unsigned Reg) AggressiveAntiDepBreaker:: -AggressiveAntiDepBreaker(MachineFunction& MFi) : +AggressiveAntiDepBreaker(MachineFunction& MFi, + TargetSubtarget::ExcludedRCVector& ExcludedRCs) : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()), TRI(MF.getTarget().getRegisterInfo()), AllocatableSet(TRI->getAllocatableSet(MF)), State(NULL), SavedState(NULL) { + /* Remove all registers from excluded RCs from the allocatable + register set. */ + for (unsigned i = 0, e = ExcludedRCs.size(); i < e; ++i) { + BitVector NotRenameable = TRI->getAllocatableSet(MF, ExcludedRCs[i]).flip(); + AllocatableSet &= NotRenameable; + } + + DEBUG(errs() << "AntiDep Renameable Registers:"); + DEBUG(for (int r = AllocatableSet.find_first(); r != -1; + r = AllocatableSet.find_next(r)) + errs() << " " << TRI->getName(r)); } AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() { diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.h b/lib/CodeGen/AggressiveAntiDepBreaker.h index c5121682bd6..fb5b869fcba 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.h +++ b/lib/CodeGen/AggressiveAntiDepBreaker.h @@ -23,6 +23,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/Target/TargetSubtarget.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" @@ -112,7 +113,7 @@ namespace llvm { /// AllocatableSet - The set of allocatable registers. /// We'll be ignoring anti-dependencies on non-allocatable registers, /// because they may not be safe to break. - const BitVector AllocatableSet; + BitVector AllocatableSet; /// State - The state used to identify and rename anti-dependence /// registers. @@ -124,7 +125,8 @@ namespace llvm { AggressiveAntiDepState *SavedState; public: - AggressiveAntiDepBreaker(MachineFunction& MFi); + AggressiveAntiDepBreaker(MachineFunction& MFi, + TargetSubtarget::ExcludedRCVector& ExcludedRCs); ~AggressiveAntiDepBreaker(); /// GetMaxTrials - As anti-dependencies are broken, additional diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 3ed61a267f7..5917e76004a 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -216,13 +216,14 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { // Check for explicit enable/disable of post-ra scheduling. TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE; + TargetSubtarget::ExcludedRCVector ExcludedRCs; if (EnablePostRAScheduler.getPosition() > 0) { if (!EnablePostRAScheduler) return false; } else { // Check that post-RA scheduling is enabled for this target. const TargetSubtarget &ST = Fn.getTarget().getSubtarget(); - if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode)) + if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, ExcludedRCs)) return false; } @@ -243,7 +244,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { (ScheduleHazardRecognizer *)new SimpleHazardRecognizer(); AntiDepBreaker *ADB = ((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ? - (AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn) : + (AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn, ExcludedRCs) : ((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ? (AntiDepBreaker *)new CriticalAntiDepBreaker(Fn) : NULL)); diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index e721a7fd680..c94f9febc50 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -17,6 +17,7 @@ #include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSubtarget.h" +#include "ARMBaseRegisterInfo.h" #include namespace llvm { @@ -129,8 +130,11 @@ protected: /// enablePostRAScheduler - True at 'More' optimization except /// for Thumb1. bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtarget::AntiDepBreakMode& mode) const { - mode = TargetSubtarget::ANTIDEP_CRITICAL; + TargetSubtarget::AntiDepBreakMode& Mode, + ExcludedRCVector& ExcludedRCs) const { + Mode = TargetSubtarget::ANTIDEP_CRITICAL; + ExcludedRCs.clear(); + ExcludedRCs.push_back(&ARM::GPRRegClass); return PostRAScheduler && OptLevel >= CodeGenOpt::Default; } diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 1c8cefa760f..f18def1f6a9 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -219,8 +219,10 @@ public: /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling /// at 'More' optimization level. bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtarget::AntiDepBreakMode& mode) const { - mode = TargetSubtarget::ANTIDEP_CRITICAL; + TargetSubtarget::AntiDepBreakMode& Mode, + ExcludedRCVector& ExcludedRCs) const { + Mode = TargetSubtarget::ANTIDEP_CRITICAL; + ExcludedRCs.clear(); return OptLevel >= CodeGenOpt::Default; } };