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Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Goodwin
2009-11-10 00:15:47 +00:00
parent 210c5d4880
commit 0855dee564
6 changed files with 37 additions and 11 deletions
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8
lib/Target/ARM/ARMSubtarget.h
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@@ -17,6 +17,7 @@
#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtarget.h"
#include "ARMBaseRegisterInfo.h"
#include <string>
namespace llvm {
@@ -129,8 +130,11 @@ protected:
/// enablePostRAScheduler - True at 'More' optimization except
/// for Thumb1.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& mode) const {
mode = TargetSubtarget::ANTIDEP_CRITICAL;
TargetSubtarget::AntiDepBreakMode& Mode,
ExcludedRCVector& ExcludedRCs) const {
Mode = TargetSubtarget::ANTIDEP_CRITICAL;
ExcludedRCs.clear();
ExcludedRCs.push_back(&ARM::GPRRegClass);
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}

6
lib/Target/X86/X86Subtarget.h
View File

@@ -219,8 +219,10 @@ public:
/// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
/// at 'More' optimization level.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& mode) const {
mode = TargetSubtarget::ANTIDEP_CRITICAL;
TargetSubtarget::AntiDepBreakMode& Mode,
ExcludedRCVector& ExcludedRCs) const {
Mode = TargetSubtarget::ANTIDEP_CRITICAL;
ExcludedRCs.clear();
return OptLevel >= CodeGenOpt::Default;
}
};