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Permit remat when a virtual register has multiple defs.

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TII::isTriviallyReMaterializable() shouldn't depend on any properties of the
register being defined by the instruction. Rematerialization is going to create
a new virtual register anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-04-20 22:14:17 +00:00
parent 344731c018
commit 08c5a347a0
1 changed files with 0 additions and 5 deletions
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5
lib/CodeGen/TargetInstrInfoImpl.cpp
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@@ -388,11 +388,6 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
if (MO.isDef() != (i == 0)) if (MO.isDef() != (i == 0))
return false; return false;
// For the def, it should be the only def of that register.
if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() ||
MRI.isLiveIn(Reg)))
return false;
// Don't allow any virtual-register uses. Rematting an instruction with // Don't allow any virtual-register uses. Rematting an instruction with
// virtual register uses would length the live ranges of the uses, which // virtual register uses would length the live ranges of the uses, which
// is not necessarily a good idea, certainly not "trivial". // is not necessarily a good idea, certainly not "trivial".