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Turn sdivs into udivs when we can prove the sign bits are clear. This
implements CodeGen/PowerPC/div-2.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23659 91177308-0d34-0410-b5e6-96231b3b80d8
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babac05a95
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094c8fcd14
lib/CodeGen/SelectionDAG
@ -501,6 +501,7 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
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SDOperand DAGCombiner::visitSDIV(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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MVT::ValueType VT = N->getValueType(0);
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
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@ -508,6 +509,15 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
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if (N0C && N1C && !N1C->isNullValue())
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return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
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N->getValueType(0));
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// If we know the sign bits of both operands are zero, strength reduce to a
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// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
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if (MaskedValueIsZero(N1, SignBit, TLI) &&
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MaskedValueIsZero(N0, SignBit, TLI))
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return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
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return SDOperand();
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}
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@ -1556,6 +1556,17 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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return N1;
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}
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break;
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case ISD::SDIV: {
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if (CombinerEnabled) break;
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// If we know the sign bits of both operands are zero, strength reduce to a
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// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
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if (MaskedValueIsZero(N2, SignBit, TLI) &&
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MaskedValueIsZero(N1, SignBit, TLI))
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return getNode(ISD::UDIV, VT, N1, N2);
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break;
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}
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case ISD::AND:
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case ISD::OR:
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