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synced 2025-03-04 05:31:51 +00:00
Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154780 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3984,15 +3984,15 @@ unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
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static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
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EVT VT = N->getValueType(0);
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assert((VT.is256BitVector() && VT.getVectorNumElements() == 4) &&
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"Unsupported vector type for VPERMQ/VPERMPD");
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unsigned NumElts = VT.getVectorNumElements();
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assert((VT.is256BitVector() && NumElts == 4) &&
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"Unsupported vector type for VPERMQ/VPERMPD");
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unsigned Mask = 0;
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for (unsigned i = 0; i != NumElts; ++i) {
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int Elt = N->getMaskElt(i);
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if (Elt < 0)
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if (Elt < 0)
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continue;
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Mask |= Elt << (i*2);
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}
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@ -6650,19 +6650,22 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG);
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if (BlendOp.getNode())
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return BlendOp;
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if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
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SmallVector<SDValue,8> permclMask;
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SmallVector<SDValue, 8> permclMask;
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for (unsigned i = 0; i != 8; ++i) {
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permclMask.push_back(DAG.getConstant((M[i] >= 0)?M[i]:0x80, MVT::i32));
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permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
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}
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return DAG.getNode(VT.isInteger()? X86ISD::VPERMD:X86ISD::VPERMPS, dl, VT,
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DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
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&permclMask[0], 8), V1);
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}
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if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
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return getTargetShuffleNode(VT.isInteger()? X86ISD::VPERMQ : X86ISD::VPERMPD, dl, VT, V1,
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if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) {
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unsigned Opcode = VT.isInteger() ? X86ISD::VPERMQ : X86ISD::VPERMPD;
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return getTargetShuffleNode(Opcode, dl, VT, V1,
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getShuffleCLImmediate(SVOp), DAG);
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}
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//===--------------------------------------------------------------------===//
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