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Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2012-04-15 23:48:57 +00:00
parent 2cb1e9dc7d
commit 095c528f30
1 changed files with 12 additions and 9 deletions
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17
lib/Target/X86/X86ISelLowering.cpp
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@ -3984,11 +3984,11 @@ unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
assert((VT.is256BitVector() && VT.getVectorNumElements() == 4) &&
"Unsupported vector type for VPERMQ/VPERMPD");
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
assert((VT.is256BitVector() && NumElts == 4) &&
"Unsupported vector type for VPERMQ/VPERMPD");
unsigned Mask = 0; unsigned Mask = 0;
for (unsigned i = 0; i != NumElts; ++i) { for (unsigned i = 0; i != NumElts; ++i) {
int Elt = N->getMaskElt(i); int Elt = N->getMaskElt(i);
@ -6650,19 +6650,22 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG); SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG);
if (BlendOp.getNode()) if (BlendOp.getNode())
return BlendOp; return BlendOp;
if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
SmallVector<SDValue, 8> permclMask; SmallVector<SDValue, 8> permclMask;
for (unsigned i = 0; i != 8; ++i) { for (unsigned i = 0; i != 8; ++i) {
permclMask.push_back(DAG.getConstant((M[i] >= 0)?M[i]:0x80, MVT::i32)); permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
} }
return DAG.getNode(VT.isInteger()? X86ISD::VPERMD:X86ISD::VPERMPS, dl, VT, return DAG.getNode(VT.isInteger()? X86ISD::VPERMD:X86ISD::VPERMPS, dl, VT,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
&permclMask[0], 8), V1); &permclMask[0], 8), V1);
} }
if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
return getTargetShuffleNode(VT.isInteger()? X86ISD::VPERMQ : X86ISD::VPERMPD, dl, VT, V1, if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) {
unsigned Opcode = VT.isInteger() ? X86ISD::VPERMQ : X86ISD::VPERMPD;
return getTargetShuffleNode(Opcode, dl, VT, V1,
getShuffleCLImmediate(SVOp), DAG); getShuffleCLImmediate(SVOp), DAG);
}
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//