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[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg

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function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2013-06-26 22:23:32 +00:00
parent 6b97ebe9a3
commit 096c0a0331
5 changed files with 20 additions and 17 deletions
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5
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -405,7 +405,10 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
Inst.addOperand(MCOperand::CreateReg(RegNo)); if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }

8
test/MC/Disassembler/Mips/mips32.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7 # CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8e 0x46 0x00 0x39 0x8e
# CHECK: cfc1 $6, $7 # CHECK: cfc1 $6, $fcc0
0x44 0x46 0x38 0x00 0x44 0x46 0x08 0x00
# CHECK: clo $6, $7 # CHECK: clo $6, $7
0x70 0xe6 0x30 0x21 0x70 0xe6 0x30 0x21
@ -167,8 +167,8 @@
# CHECK: clz $6, $7 # CHECK: clz $6, $7
0x70 0xe6 0x30 0x20 0x70 0xe6 0x30 0x20
# CHECK: ctc1 $6, $7 # CHECK: ctc1 $6, $fcc0
0x44 0xc6 0x38 0x00 0x44 0xc6 0x08 0x00
# CHECK: cvt.d.s $f6, $f7 # CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa1 0x46 0x00 0x39 0xa1

8
test/MC/Disassembler/Mips/mips32_le.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7 # CHECK: ceil.w.s $f6, $f7
0x8e 0x39 0x00 0x46 0x8e 0x39 0x00 0x46
# CHECK: cfc1 $6, $7 # CHECK: cfc1 $6, $fcc0
0x00 0x38 0x46 0x44 0x00 0x08 0x46 0x44
# CHECK: clo $6, $7 # CHECK: clo $6, $7
0x21 0x30 0xe6 0x70 0x21 0x30 0xe6 0x70
@ -167,8 +167,8 @@
# CHECK: clz $6, $7 # CHECK: clz $6, $7
0x20 0x30 0xe6 0x70 0x20 0x30 0xe6 0x70
# CHECK: ctc1 $6, $7 # CHECK: ctc1 $6, $fcc0
0x00 0x38 0xc6 0x44 0x00 0x08 0xc6 0x44
# CHECK: cvt.d.s $f6, $f7 # CHECK: cvt.d.s $f6, $f7
0xa1 0x39 0x00 0x46 0xa1 0x39 0x00 0x46

8
test/MC/Disassembler/Mips/mips32r2.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7 # CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8e 0x46 0x00 0x39 0x8e
# CHECK: cfc1 $6, $7 # CHECK: cfc1 $6, $fcc0
0x44 0x46 0x38 0x00 0x44 0x46 0x08 0x00
# CHECK: clo $6, $7 # CHECK: clo $6, $7
0x70 0xe6 0x30 0x21 0x70 0xe6 0x30 0x21
@ -167,8 +167,8 @@
# CHECK: clz $6, $7 # CHECK: clz $6, $7
0x70 0xe6 0x30 0x20 0x70 0xe6 0x30 0x20
# CHECK: ctc1 $6, $7 # CHECK: ctc1 $6, $fcc0
0x44 0xc6 0x38 0x00 0x44 0xc6 0x08 0x00
# CHECK: cvt.d.s $f6, $f7 # CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa1 0x46 0x00 0x39 0xa1

8
test/MC/Disassembler/Mips/mips32r2_le.txt
View File

@ -158,8 +158,8 @@
# CHECK: ceil.w.s $f6, $f7 # CHECK: ceil.w.s $f6, $f7
0x8e 0x39 0x00 0x46 0x8e 0x39 0x00 0x46
# CHECK: cfc1 $6, $7 # CHECK: cfc1 $6, $fcc0
0x00 0x38 0x46 0x44 0x00 0x08 0x46 0x44
# CHECK: clo $6, $7 # CHECK: clo $6, $7
0x21 0x30 0xe6 0x70 0x21 0x30 0xe6 0x70
@ -167,8 +167,8 @@
# CHECK: clz $6, $7 # CHECK: clz $6, $7
0x20 0x30 0xe6 0x70 0x20 0x30 0xe6 0x70
# CHECK: ctc1 $6, $7 # CHECK: ctc1 $6, $fcc0
0x00 0x38 0xc6 0x44 0x00 0x08 0xc6 0x44
# CHECK: cvt.d.s $f6, $f7 # CHECK: cvt.d.s $f6, $f7
0xa1 0x39 0x00 0x46 0xa1 0x39 0x00 0x46