mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add support patterns to many load and store instructions which will
hopefully use patterns in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
d8fe3b3272
commit
0976122abc
@ -58,23 +58,27 @@ class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL,
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// 1.7.4 D-Form
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class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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let Pattern = pattern;
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> A;
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bits<5> B;
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bits<16> C;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: I<opcode, OL, asmstr, itin> {
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class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> A;
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bits<16> C;
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bits<5> B;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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@ -99,12 +103,13 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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}
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// Currently we make the use/def reg distinction in ISel, not tablegen
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class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_1<opcode, OL, asmstr, itin>;
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class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern>;
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class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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: I<opcode, OL, asmstr, itin> {
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bits<5> B;
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bits<5> A;
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bits<16> C;
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@ -116,8 +121,9 @@ class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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let Inst{16-31} = C;
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}
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class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_1<opcode, OL, asmstr, itin> {
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class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern> {
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let A = 0;
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let B = 0;
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let C = 0;
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@ -150,22 +156,26 @@ class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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let L = PPC64;
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}
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class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_1<opcode, OL, asmstr, itin> {
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class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern> {
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}
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class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: DForm_1<opcode, OL, asmstr, itin> {
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class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern> {
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}
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// 1.7.5 DS-Form
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class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
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InstrItinClass itin>
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RST;
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bits<14> DS;
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bits<5> RA;
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let Pattern = pattern;
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let Inst{6-10} = RST;
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let Inst{11-15} = RA;
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let Inst{16-29} = DS;
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@ -173,17 +183,19 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
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}
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class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: DSForm_1<opcode, xo, OL, asmstr, itin>;
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InstrItinClass itin, list<dag> pattern>
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: DSForm_1<opcode, xo, OL, asmstr, itin, pattern>;
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo,
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dag OL, string asmstr, InstrItinClass itin>
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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bits<5> RST;
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bits<5> A;
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bits<5> B;
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let Pattern = pattern;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = RST;
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@ -214,8 +226,8 @@ class XForm_base_r3xo_swapped
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class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin>;
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
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class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -224,8 +236,8 @@ class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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}
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class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin>;
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
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class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -279,20 +291,19 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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}
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class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
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}
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class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
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let A = 0;
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let Pattern = pattern;
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}
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class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
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}
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// 1.7.7 XL-Form
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@ -255,17 +255,23 @@ let isCall = 1,
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//
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let isLoad = 1 in {
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def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lbz $rD, $disp($rA)", LdStGeneral>;
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"lbz $rD, $disp($rA)", LdStGeneral,
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[]>;
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def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lha $rD, $disp($rA)", LdStLHA>;
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"lha $rD, $disp($rA)", LdStLHA,
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[]>;
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def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lhz $rD, $disp($rA)", LdStGeneral>;
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"lhz $rD, $disp($rA)", LdStGeneral,
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[]>;
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def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lmw $rD, $disp($rA)", LdStLMW>;
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"lmw $rD, $disp($rA)", LdStLMW,
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[]>;
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def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lwz $rD, $disp($rA)", LdStGeneral>;
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"lwz $rD, $disp($rA)", LdStGeneral,
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[]>;
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def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lwzu $rD, $disp($rA)", LdStGeneral>;
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"lwzu $rD, $disp($rA)", LdStGeneral,
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[]>;
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}
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def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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@ -297,15 +303,20 @@ def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
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[(set GPRC:$rD, imm16Shifted:$imm)]>;
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let isStore = 1 in {
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def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stmw $rS, $disp($rA)", LdStLMW>;
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"stmw $rS, $disp($rA)", LdStLMW,
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[]>;
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def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
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"stb $rS, $disp($rA)", LdStGeneral>;
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"stb $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
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"sth $rS, $disp($rA)", LdStGeneral>;
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"sth $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
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"stw $rS, $disp($rA)", LdStGeneral>;
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"stw $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stwu $rS, $disp($rA)", LdStGeneral>;
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"stwu $rS, $disp($rA)", LdStGeneral,
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[]>;
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}
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def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2", IntGeneral,
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@ -325,7 +336,8 @@ def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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[(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
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def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
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def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
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[]>;
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def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
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"cmpi $crD, $L, $rA, $imm", IntCompare>;
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def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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@ -340,30 +352,38 @@ def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
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let isLoad = 1 in {
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def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
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"lfs $rD, $disp($rA)", LdStLFDU>;
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"lfs $rD, $disp($rA)", LdStLFDU,
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[]>;
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def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
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"lfd $rD, $disp($rA)", LdStLFD>;
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"lfd $rD, $disp($rA)", LdStLFD,
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[]>;
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}
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let isStore = 1 in {
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def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
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"stfs $rS, $disp($rA)", LdStUX>;
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"stfs $rS, $disp($rA)", LdStUX,
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[]>;
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def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
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"stfd $rS, $disp($rA)", LdStUX>;
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"stfd $rS, $disp($rA)", LdStUX,
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[]>;
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}
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// DS-Form instructions. Load/Store instructions available in PPC-64
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//
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let isLoad = 1 in {
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def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
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"lwa $rT, $DS($rA)", LdStLWA,
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[]>, isPPC64;
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def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)", LdStLD>, isPPC64;
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"ld $rT, $DS($rA)", LdStLD,
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[]>, isPPC64;
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}
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let isStore = 1 in {
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def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"std $rT, $DS($rA)", LdStSTD>, isPPC64;
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"std $rT, $DS($rA)", LdStSTD,
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[]>, isPPC64;
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def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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"stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
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"stdu $rT, $DS($rA)", LdStSTD,
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[]>, isPPC64;
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}
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// X-Form instructions. Most instructions that perform an operation on a
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@ -371,30 +391,42 @@ def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
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//
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let isLoad = 1 in {
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def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lbzx $dst, $base, $index", LdStGeneral>;
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"lbzx $dst, $base, $index", LdStGeneral,
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[]>;
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def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lhax $dst, $base, $index", LdStLHA>;
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"lhax $dst, $base, $index", LdStLHA,
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[]>;
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def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lhzx $dst, $base, $index", LdStGeneral>;
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"lhzx $dst, $base, $index", LdStGeneral,
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[]>;
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def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwax $dst, $base, $index", LdStLHA>, isPPC64;
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"lwax $dst, $base, $index", LdStLHA,
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[]>, isPPC64;
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def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwzx $dst, $base, $index", LdStGeneral>;
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"lwzx $dst, $base, $index", LdStGeneral,
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[]>;
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def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index", LdStLD>, isPPC64;
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"ldx $dst, $base, $index", LdStLD,
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[]>, isPPC64;
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def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvebx $vD, $base, $rA", LdStGeneral>;
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"lvebx $vD, $base, $rA", LdStGeneral,
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[]>;
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def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvehx $vD, $base, $rA", LdStGeneral>;
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"lvehx $vD, $base, $rA", LdStGeneral,
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[]>;
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def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvewx $vD, $base, $rA", LdStGeneral>;
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"lvewx $vD, $base, $rA", LdStGeneral,
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[]>;
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def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvx $vD, $base, $rA", LdStGeneral>;
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral>;
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def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral>;
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"lvx $vD, $base, $rA", LdStGeneral,
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[]>;
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}
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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"lvsl $vD, $base, $rA", LdStGeneral,
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[]>;
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def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvsl $vD, $base, $rA", LdStGeneral,
|
||||
[]>;
|
||||
def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
"nand $rA, $rS, $rB", IntGeneral,
|
||||
[(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
|
||||
@ -454,25 +486,35 @@ def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
[(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
|
||||
let isStore = 1 in {
|
||||
def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stbx $rS, $rA, $rB", LdStGeneral>;
|
||||
"stbx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"sthx $rS, $rA, $rB", LdStGeneral>;
|
||||
"sthx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stwx $rS, $rA, $rB", LdStGeneral>;
|
||||
"stwx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stwux $rS, $rA, $rB", LdStGeneral>;
|
||||
"stwux $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
|
||||
"stdx $rS, $rA, $rB", LdStSTD,
|
||||
[]>, isPPC64;
|
||||
def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
|
||||
"stdux $rS, $rA, $rB", LdStSTD,
|
||||
[]>, isPPC64;
|
||||
def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvebx $rS, $rA, $rB", LdStGeneral>;
|
||||
"stvebx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvehx $rS, $rA, $rB", LdStGeneral>;
|
||||
"stvehx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvewx $rS, $rA, $rB", LdStGeneral>;
|
||||
"stvewx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvx $rS, $rA, $rB", LdStGeneral>;
|
||||
"stvx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
}
|
||||
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
|
||||
"srawi $rA, $rS, $SH", IntShift,
|
||||
@ -510,9 +552,11 @@ def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
|
||||
|
||||
let isLoad = 1 in {
|
||||
def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lfsx $dst, $base, $index", LdStLFDU>;
|
||||
"lfsx $dst, $base, $index", LdStLFDU,
|
||||
[]>;
|
||||
def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lfdx $dst, $base, $index", LdStLFDU>;
|
||||
"lfdx $dst, $base, $index", LdStLFDU,
|
||||
[]>;
|
||||
}
|
||||
def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
|
||||
"fcfid $frD, $frB", FPGeneral,
|
||||
@ -567,9 +611,11 @@ def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
|
||||
|
||||
let isStore = 1 in {
|
||||
def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfsx $frS, $rA, $rB", LdStUX>;
|
||||
"stfsx $frS, $rA, $rB", LdStUX,
|
||||
[]>;
|
||||
def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfdx $frS, $rA, $rB", LdStUX>;
|
||||
"stfdx $frS, $rA, $rB", LdStUX,
|
||||
[]>;
|
||||
}
|
||||
|
||||
// XL-Form instructions. condition register logical ops.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user