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[mips][msa] Define registers using foreach

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No functional change


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2013-08-21 08:48:25 +00:00
parent 171ac8ca17
commit 099e5328fc
1 changed files with 3 additions and 32 deletions
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35
lib/Target/Mips/MipsRegisterInfo.td
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@ -173,38 +173,9 @@ let Namespace = "Mips" in {
/// Mips MSA registers
/// MSA and FPU cannot both be present unless the FPU has 64-bit registers
def W0 : AFPR128<0, "w0", [D0_64]>, DwarfRegNum<[32]>;
def W1 : AFPR128<1, "w1", [D1_64]>, DwarfRegNum<[33]>;
def W2 : AFPR128<2, "w2", [D2_64]>, DwarfRegNum<[34]>;
def W3 : AFPR128<3, "w3", [D3_64]>, DwarfRegNum<[35]>;
def W4 : AFPR128<4, "w4", [D4_64]>, DwarfRegNum<[36]>;
def W5 : AFPR128<5, "w5", [D5_64]>, DwarfRegNum<[37]>;
def W6 : AFPR128<6, "w6", [D6_64]>, DwarfRegNum<[38]>;
def W7 : AFPR128<7, "w7", [D7_64]>, DwarfRegNum<[39]>;
def W8 : AFPR128<8, "w8", [D8_64]>, DwarfRegNum<[40]>;
def W9 : AFPR128<9, "w9", [D9_64]>, DwarfRegNum<[41]>;
def W10 : AFPR128<10, "w10", [D10_64]>, DwarfRegNum<[42]>;
def W11 : AFPR128<11, "w11", [D11_64]>, DwarfRegNum<[43]>;
def W12 : AFPR128<12, "w12", [D12_64]>, DwarfRegNum<[44]>;
def W13 : AFPR128<13, "w13", [D13_64]>, DwarfRegNum<[45]>;
def W14 : AFPR128<14, "w14", [D14_64]>, DwarfRegNum<[46]>;
def W15 : AFPR128<15, "w15", [D15_64]>, DwarfRegNum<[47]>;
def W16 : AFPR128<16, "w16", [D16_64]>, DwarfRegNum<[48]>;
def W17 : AFPR128<17, "w17", [D17_64]>, DwarfRegNum<[49]>;
def W18 : AFPR128<18, "w18", [D18_64]>, DwarfRegNum<[50]>;
def W19 : AFPR128<19, "w19", [D19_64]>, DwarfRegNum<[51]>;
def W20 : AFPR128<20, "w20", [D20_64]>, DwarfRegNum<[52]>;
def W21 : AFPR128<21, "w21", [D21_64]>, DwarfRegNum<[53]>;
def W22 : AFPR128<22, "w22", [D22_64]>, DwarfRegNum<[54]>;
def W23 : AFPR128<23, "w23", [D23_64]>, DwarfRegNum<[55]>;
def W24 : AFPR128<24, "w24", [D24_64]>, DwarfRegNum<[56]>;
def W25 : AFPR128<25, "w25", [D25_64]>, DwarfRegNum<[57]>;
def W26 : AFPR128<26, "w26", [D26_64]>, DwarfRegNum<[58]>;
def W27 : AFPR128<27, "w27", [D27_64]>, DwarfRegNum<[59]>;
def W28 : AFPR128<28, "w28", [D28_64]>, DwarfRegNum<[60]>;
def W29 : AFPR128<29, "w29", [D29_64]>, DwarfRegNum<[61]>;
def W30 : AFPR128<30, "w30", [D30_64]>, DwarfRegNum<[62]>;
def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>;
foreach I = 0-31 in
def W#I : AFPR128<0, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
DwarfRegNum<[!add(I, 32)]>;
// Hi/Lo registers
def HI0 : Register<"ac0">, DwarfRegNum<[64]>;