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AVX-512: decoder for AVX-512, made by Alexey Bader.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
2013-12-25 11:40:51 +00:00
parent 97d9733a38
commit 09a63715ce
7 changed files with 401 additions and 127 deletions
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37
lib/Target/X86/Disassembler/X86Disassembler.cpp
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@ -418,13 +418,22 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
Opcode == X86::VGATHERDPSYrm ||
Opcode == X86::VGATHERQPSYrm ||
Opcode == X86::VGATHERDPDZrm ||
Opcode == X86::VPGATHERDQZrm ||
Opcode == X86::VPGATHERQQYrm ||
Opcode == X86::VPGATHERDDYrm ||
Opcode == X86::VPGATHERQDYrm);
if (IndexIs128 || IndexIs256) {
bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
Opcode == X86::VGATHERDPSZrm ||
Opcode == X86::VGATHERQPSZrm ||
Opcode == X86::VPGATHERQQZrm ||
Opcode == X86::VPGATHERDDZrm ||
Opcode == X86::VPGATHERQDZrm);
if (IndexIs128 || IndexIs256 || IndexIs512) {
unsigned IndexOffset = insn.sibIndex -
(insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
SIBIndex IndexBase = IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
insn.sibIndex = (SIBIndex)(IndexBase +
(insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
}
@ -565,6 +574,9 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
case TYPE_XMM128:
case TYPE_XMM256:
case TYPE_XMM512:
case TYPE_VK1:
case TYPE_VK8:
case TYPE_VK16:
case TYPE_DEBUGREG:
case TYPE_CONTROLREG:
return translateRMRegister(mcInst, insn);
@ -596,7 +608,7 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
///
/// @param mcInst - The MCInst to append to.
/// @param stackPos - The stack position to translate.
/// @return - 0 on success; nonzero otherwise.
/// @return - false on success; true otherwise.
static bool translateFPRegister(MCInst &mcInst,
uint8_t stackPos) {
if (stackPos >= 8) {
@ -609,6 +621,23 @@ static bool translateFPRegister(MCInst &mcInst,
return false;
}
/// translateMaskRegister - Translates a 3-bit mask register number to
/// LLVM form, and appends it to an MCInst.
///
/// @param mcInst - The MCInst to append to.
/// @param maskRegNum - Number of mask register from 0 to 7.
/// @return - false on success; true otherwise.
static bool translateMaskRegister(MCInst &mcInst,
uint8_t maskRegNum) {
if (maskRegNum >= 8) {
debug("Invalid mask register number");
return true;
}
mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
return false;
}
/// translateOperand - Translates an operand stored in an internal instruction
/// to LLVM's format and appends it to an MCInst.
///
@ -626,6 +655,8 @@ static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
case ENCODING_REG:
translateRegister(mcInst, insn.reg);
return false;
case ENCODING_WRITEMASK:
return translateMaskRegister(mcInst, insn.writemask);
case ENCODING_RM:
return translateRM(mcInst, operand, insn, Dis);
case ENCODING_CB: