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Use 16 byte stack alignment for NaCl on ARM

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NaCl's ARM ABI uses 16 byte stack alignment, so set that in
ARMSubtarget.cpp.

Using 16 byte alignment exposes an issue in code generation in which a
varargs function leaves a 4 byte gap between the values of r1-r3 saved
to the stack and the following arguments that were passed on the
stack.  (Previously, this code only needed to support 4 byte and 8
byte alignment.)

With this issue, llc generated:

varargs_func:
        sub     sp, sp, #16
        push    {lr}
        sub     sp, sp, #12
        add     r0, sp, #16   // Should be 20
        stm     r0, {r1, r2, r3}
        ldr     r0, .LCPI0_0  // Address of va_list
        add     r1, sp, #16
        str     r1, [r0]
        bl      external_func

Fix the bug by checking for "Align > 4".  Also simplify the code by
using OffsetToAlignment(), and update comments.

Differential Revision: http://llvm-reviews.chandlerc.com/D2677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201497 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mark Seaborn 2014-02-16 18:59:48 +00:00
parent 2ced33808e
commit 09d1d540c8
4 changed files with 38 additions and 6 deletions
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9
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -2756,11 +2756,11 @@ ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
ArgRegsSize = NumGPRs * 4;
// If parameter is split between stack and GPRs...
if (NumGPRs && Align == 8 &&
if (NumGPRs && Align > 4 &&
(ArgRegsSize < ArgSize ||
InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
// Add padding for part of param recovered from GPRs, so
// its last byte must be at address K*8 - 1.
// Add padding for part of param recovered from GPRs. For example,
// if Align == 8, its last byte must be at address K*8 - 1.
// We need to do it, since remained (stack) part of parameter has
// stack alignment, and we need to "attach" "GPRs head" without gaps
// to it:
@ -2770,8 +2770,7 @@ ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
//
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned Padding =
((ArgRegsSize + AFI->getArgRegsSaveSize() + Align - 1) & ~(Align-1)) -
(ArgRegsSize + AFI->getArgRegsSaveSize());
OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
ArgRegsSaveSize = ArgRegsSize + Padding;
} else
// We don't need to extend regs save size for byval parameters if they

2
lib/Target/ARM/ARMMachineFunctionInfo.h
View File

@ -38,7 +38,7 @@ class ARMFunctionInfo : public MachineFunctionInfo {
/// StByValParamsPadding - For parameter that is split between
/// GPRs and memory; while recovering GPRs part, when
/// StackAlignment == 8, and GPRs-part-size mod 8 != 0,
/// StackAlignment > 4, and GPRs-part-size mod StackAlignment != 0,
/// we need to insert gap before parameter start address. It allows to
/// "attach" GPR-part to the part that was passed via stack.
unsigned StByValParamsPadding;

2
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -210,6 +210,8 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
if (isAAPCS_ABI())
stackAlignment = 8;
if (isTargetNaCl())
stackAlignment = 16;
UseMovt = hasV6T2Ops() && ArmUseMOVT;

31
test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll Normal file
View File

@ -0,0 +1,31 @@
; RUN: llc < %s -mtriple=arm-nacl-gnueabi | FileCheck %s
declare void @llvm.va_start(i8*)
declare void @external_func(i8*)
@va_list = external global i8*
; On ARM, varargs arguments are passed in r0-r3 with the rest on the
; stack. A varargs function must therefore spill rN-r3 just below the
; function's initial stack pointer.
;
; This test checks for a bug in which a gap was left between the spill
; area and varargs arguments on the stack when using 16 byte stack
; alignment.
define void @varargs_func(i32 %arg1, ...) {
call void @llvm.va_start(i8* bitcast (i8** @va_list to i8*))
call void @external_func(i8* bitcast (i8** @va_list to i8*))
ret void
}
; CHECK-LABEL: varargs_func:
; Reserve space for the varargs save area. This currently reserves
; more than enough (16 bytes rather than the 12 bytes needed).
; CHECK: sub sp, sp, #16
; CHECK: push {lr}
; Align the stack pointer to a multiple of 16.
; CHECK: sub sp, sp, #12
; Calculate the address of the varargs save area and save varargs
; arguments into it.
; CHECK-NEXT: add r0, sp, #20
; CHECK-NEXT: stm r0, {r1, r2, r3}