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Thumb2 M-class MSR instruction support changes
This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216874 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin
parent
7948290532
commit
09e28e39f0
@ -4013,15 +4013,17 @@ def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
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//
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// This MRS has a mask field in bits 7-0 and can take more values than
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// the A/R class (a full msr_mask).
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def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
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"mrs", "\t$Rd, $mask", []>,
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def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
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"mrs", "\t$Rd, $SYSm", []>,
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Requires<[IsThumb,IsMClass]> {
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bits<4> Rd;
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bits<8> mask;
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bits<8> SYSm;
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let Inst{31-12} = 0b11110011111011111000;
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let Inst{11-8} = Rd;
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let Inst{19-16} = 0b1111;
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let Inst{7-0} = mask;
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let Inst{7-0} = SYSm;
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let Unpredictable{20-16} = 0b11111;
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let Unpredictable{13} = 0b1;
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}
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@ -4077,7 +4079,13 @@ def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
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let Inst{20} = 0b0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = 0b1000;
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let Inst{11-0} = SYSm;
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let Inst{11-10} = SYSm{11-10};
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let Inst{9-8} = 0b00;
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let Inst{7-0} = SYSm{7-0};
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let Unpredictable{20} = 0b1;
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let Unpredictable{13} = 0b1;
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let Unpredictable{9-8} = 0b11;
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}
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@ -265,6 +265,9 @@ class ARMAsmParser : public MCTargetAsmParser {
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bool hasARM() const {
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return !(STI.getFeatureBits() & ARM::FeatureNoARM);
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}
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bool hasThumb2DSP() const {
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return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
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}
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void SwitchMode() {
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uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
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@ -3928,9 +3931,6 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
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// should really only be allowed when writing a special register. Note
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// they get dropped in the MRS instruction reading a special register as
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// the SYSm field is only 8 bits.
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//
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// FIXME: the _g and _nzcvqg versions are only allowed if the processor
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// includes the DSP extension but that is not checked.
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.Case("apsr", 0x800)
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.Case("apsr_nzcvq", 0x800)
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.Case("apsr_g", 0x400)
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@ -3962,6 +3962,11 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
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if (FlagsVal == ~0U)
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return MatchOperand_NoMatch;
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if (!hasThumb2DSP() && (FlagsVal & 0x400))
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// The _g and _nzcvqg versions are only valid if the DSP extension is
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// available.
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return MatchOperand_NoMatch;
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if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
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// basepri, basepri_max and faultmask only valid for V7m.
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return MatchOperand_NoMatch;
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@ -3976,6 +3976,7 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
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.getFeatureBits();
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if (FeatureBits & ARM::FeatureMClass) {
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@ -4006,17 +4007,25 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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return MCDisassembler::Fail;
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}
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// The ARMv7-M architecture has an additional 2-bit mask value in the MSR
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// instruction (bits {11,10}). The mask is used only with apsr, iapsr,
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// eapsr and xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates
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// if the NZCVQ bits should be moved by the instruction. Bit mask{0}
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// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
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// only if the processor includes the DSP extension.
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if ((FeatureBits & ARM::HasV7Ops) && Inst.getOpcode() == ARM::t2MSR_M) {
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unsigned Mask = (Val >> 10) & 3;
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if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
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(!(FeatureBits & ARM::FeatureDSPThumb2) && Mask == 1))
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return MCDisassembler::Fail;
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if (Inst.getOpcode() == ARM::t2MSR_M) {
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unsigned Mask = fieldFromInstruction(Val, 10, 2);
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if (!(FeatureBits & ARM::HasV7Ops)) {
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// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
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// unpredictable.
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if (Mask != 2)
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S = MCDisassembler::SoftFail;
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}
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else {
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// The ARMv7-M architecture stores an additional 2-bit mask value in
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// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
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// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
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// the NZCVQ bits should be moved by the instruction. Bit mask{0}
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// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
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// only if the processor includes the DSP extension.
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if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
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(!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
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S = MCDisassembler::SoftFail;
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}
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}
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} else {
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// A/R class
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@ -4024,7 +4033,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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return MCDisassembler::Fail;
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}
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Inst.addOperand(MCOperand::CreateImm(Val));
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return MCDisassembler::Success;
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return S;
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}
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static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
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@ -807,52 +807,56 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
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const MCOperand &Op = MI->getOperand(OpNum);
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unsigned SpecRegRBit = Op.getImm() >> 4;
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unsigned Mask = Op.getImm() & 0xf;
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uint64_t FeatureBits = getAvailableFeatures();
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if (getAvailableFeatures() & ARM::FeatureMClass) {
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if (FeatureBits & ARM::FeatureMClass) {
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unsigned SYSm = Op.getImm();
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unsigned Opcode = MI->getOpcode();
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// For reads of the special registers ignore the "mask encoding" bits
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// which are only for writes.
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if (Opcode == ARM::t2MRS_M)
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SYSm &= 0xff;
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// For writes, handle extended mask bits if the DSP extension is present.
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if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
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switch (SYSm) {
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case 0x400: O << "apsr_g"; return;
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case 0xc00: O << "apsr_nzcvqg"; return;
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case 0x401: O << "iapsr_g"; return;
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case 0xc01: O << "iapsr_nzcvqg"; return;
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case 0x402: O << "eapsr_g"; return;
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case 0xc02: O << "eapsr_nzcvqg"; return;
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case 0x403: O << "xpsr_g"; return;
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case 0xc03: O << "xpsr_nzcvqg"; return;
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}
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}
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// Handle the basic 8-bit mask.
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SYSm &= 0xff;
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if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
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// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
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// alias for MSR APSR_nzcvq.
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switch (SYSm) {
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case 0: O << "apsr_nzcvq"; return;
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case 1: O << "iapsr_nzcvq"; return;
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case 2: O << "eapsr_nzcvq"; return;
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case 3: O << "xpsr_nzcvq"; return;
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}
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}
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switch (SYSm) {
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default: llvm_unreachable("Unexpected mask value!");
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case 0:
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case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
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case 0x400: O << "apsr_g"; return;
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case 0xc00: O << "apsr_nzcvqg"; return;
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case 1:
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case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
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case 0x401: O << "iapsr_g"; return;
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case 0xc01: O << "iapsr_nzcvqg"; return;
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case 2:
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case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
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case 0x402: O << "eapsr_g"; return;
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case 0xc02: O << "eapsr_nzcvqg"; return;
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case 3:
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case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
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case 0x403: O << "xpsr_g"; return;
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case 0xc03: O << "xpsr_nzcvqg"; return;
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case 5:
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case 0x805: O << "ipsr"; return;
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case 6:
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case 0x806: O << "epsr"; return;
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case 7:
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case 0x807: O << "iepsr"; return;
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case 8:
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case 0x808: O << "msp"; return;
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case 9:
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case 0x809: O << "psp"; return;
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case 0x10:
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case 0x810: O << "primask"; return;
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case 0x11:
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case 0x811: O << "basepri"; return;
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case 0x12:
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case 0x812: O << "basepri_max"; return;
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case 0x13:
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case 0x813: O << "faultmask"; return;
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case 0x14:
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case 0x814: O << "control"; return;
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case 0: O << "apsr"; return;
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case 1: O << "iapsr"; return;
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case 2: O << "eapsr"; return;
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case 3: O << "xpsr"; return;
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case 5: O << "ipsr"; return;
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case 6: O << "epsr"; return;
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case 7: O << "iepsr"; return;
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case 8: O << "msp"; return;
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case 9: O << "psp"; return;
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case 16: O << "primask"; return;
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case 17: O << "basepri"; return;
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case 18: O << "basepri_max"; return;
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case 19: O << "faultmask"; return;
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case 20: O << "control"; return;
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}
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}
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@ -1,7 +1,7 @@
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@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V6M %s
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@ RUN: llvm-mc -triple=thumbv7m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
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.syntax unified
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.globl _func
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ These tests test instruction encodings specific to v6m & v7m (FeatureMClass).
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@ -40,20 +40,12 @@
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msr apsr, r0
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msr apsr_nzcvq, r0
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msr apsr_g, r0
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msr apsr_nzcvqg, r0
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msr iapsr, r0
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msr iapsr_nzcvq, r0
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msr iapsr_g, r0
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msr iapsr_nzcvqg, r0
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msr eapsr, r0
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msr eapsr_nzcvq, r0
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msr eapsr_g, r0
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msr eapsr_nzcvqg, r0
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msr xpsr, r0
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msr xpsr_nzcvq, r0
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msr xpsr_g, r0
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msr xpsr_nzcvqg, r0
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msr ipsr, r0
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msr epsr, r0
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msr iepsr, r0
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@ -62,22 +54,22 @@
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msr primask, r0
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msr control, r0
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@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
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@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
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@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]
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@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]
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@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]
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@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]
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@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
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@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
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@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
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@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88]
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@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88]
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53
test/MC/ARM/thumbv7em.s
Normal file
53
test/MC/ARM/thumbv7em.s
Normal file
@ -0,0 +1,53 @@
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@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv7m -show-encoding 2>&1 < %s | FileCheck --check-prefix=CHECK-V7M %s
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.syntax unified
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ These tests test instruction encodings specific to ARMv7E-M.
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@------------------------------------------------------------------------------
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@ MSR
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@------------------------------------------------------------------------------
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msr apsr_g, r0
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msr apsr_nzcvqg, r0
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msr iapsr_g, r0
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msr iapsr_nzcvqg, r0
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msr eapsr_g, r0
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msr eapsr_nzcvqg, r0
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msr xpsr_g, r0
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msr xpsr_nzcvqg, r0
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@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
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@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
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@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]
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@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]
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@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]
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@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]
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@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
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@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr apsr_g, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr apsr_nzcvqg, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
|
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@ CHECK-V7M-NEXT: msr iapsr_g, r0
|
||||
@ CHECK-V7M-NEXT: ^
|
||||
@ CHECK-V7M: error: invalid operand for instruction
|
||||
@ CHECK-V7M-NEXT: msr iapsr_nzcvqg, r0
|
||||
@ CHECK-V7M-NEXT: ^
|
||||
@ CHECK-V7M: error: invalid operand for instruction
|
||||
@ CHECK-V7M-NEXT: msr eapsr_g, r0
|
||||
@ CHECK-V7M-NEXT: ^
|
||||
@ CHECK-V7M: error: invalid operand for instruction
|
||||
@ CHECK-V7M-NEXT: msr eapsr_nzcvqg, r0
|
||||
@ CHECK-V7M-NEXT: ^
|
||||
@ CHECK-V7M: error: invalid operand for instruction
|
||||
@ CHECK-V7M-NEXT: msr xpsr_g, r0
|
||||
@ CHECK-V7M-NEXT: ^
|
||||
@ CHECK-V7M: error: invalid operand for instruction
|
||||
@ CHECK-V7M-NEXT: msr xpsr_nzcvqg, r0
|
||||
@ CHECK-V7M-NEXT: ^
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: not llvm-mc -disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 2>&1 | FileCheck %s
|
||||
# RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck --check-prefix=CHECK %s
|
||||
# RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# Undefined encodings for mrs
|
||||
@ -14,18 +15,18 @@
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# invalid mask = '00'
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK: warning: potentially undefined instruction encoding
|
||||
# CHECK-NEXT: [0x80 0xf3 0x00 0x80]
|
||||
[0x80 0xf3 0x00 0x80]
|
||||
|
||||
# invalid mask = '11' with SYSm not in {0..3}
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK-NEXT: [0x80 0xf3 0x04 0x8c]
|
||||
[0x80 0xf3 0x04 0x8c]
|
||||
# CHECK: warning: potentially undefined instruction encoding
|
||||
# CHECK-NEXT: [0x80 0xf3 0x05 0x8c]
|
||||
[0x80 0xf3 0x05 0x8c]
|
||||
|
||||
# invalid mask = '01' (Cortex-M3 does not have the DSP extension)
|
||||
# CHECK: warning: invalid instruction encoding
|
||||
# CHECK-NEXT: [0x80 0xf3 0x00 0x84]
|
||||
# invalid mask = '01' (ThumbV7M does not have the DSP extension)
|
||||
# CHECK-V7M: warning: potentially undefined instruction encoding
|
||||
# CHECK-V7M-NEXT: [0x80 0xf3 0x00 0x84]
|
||||
[0x80 0xf3 0x00 0x84]
|
||||
|
||||
# invalid SYSm
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m4 | FileCheck %s
|
||||
# RUN: llvm-mc --disassemble %s -triple=thumbv7em | FileCheck %s
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# MRS
|
||||
@ -39,7 +39,7 @@
|
||||
# MSR
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# CHECK: msr apsr, r0
|
||||
# CHECK: msr apsr_nzcvq, r0
|
||||
# CHECK: msr apsr_g, r0
|
||||
# CHECK: msr apsr_nzcvqg, r0
|
||||
|
||||
@ -47,7 +47,7 @@
|
||||
0x80 0xf3 0x00 0x84
|
||||
0x80 0xf3 0x00 0x8c
|
||||
|
||||
# CHECK: msr iapsr, r0
|
||||
# CHECK: msr iapsr_nzcvq, r0
|
||||
# CHECK: msr iapsr_g, r0
|
||||
# CHECK: msr iapsr_nzcvqg, r0
|
||||
|
||||
@ -55,7 +55,7 @@
|
||||
0x80 0xf3 0x01 0x84
|
||||
0x80 0xf3 0x01 0x8c
|
||||
|
||||
# CHECK: msr eapsr, r0
|
||||
# CHECK: msr eapsr_nzcvq, r0
|
||||
# CHECK: msr eapsr_g, r0
|
||||
# CHECK: msr eapsr_nzcvqg, r0
|
||||
|
||||
@ -63,7 +63,7 @@
|
||||
0x80 0xf3 0x02 0x84
|
||||
0x80 0xf3 0x02 0x8c
|
||||
|
||||
# CHECK: msr xpsr, r0
|
||||
# CHECK: msr xpsr_nzcvq, r0
|
||||
# CHECK: msr xpsr_g, r0
|
||||
# CHECK: msr xpsr_nzcvqg, r0
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user