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[mips] Refactor load/store left/right and load-link and store-conditional

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instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-21 23:01:24 +00:00
parent 16164657d8
commit 0a57dc1d14
2 changed files with 51 additions and 78 deletions
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33
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -142,28 +142,25 @@ defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>;
/// load/store left/right
let isCodeGenOnly = 1 in {
defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>;
defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>;
defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>;
defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>;
defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
}
defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>;
defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>;
defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>;
defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>;
defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
/// Load-linked, Store-conditional
def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
Requires<[NotN64, HasStdEnc]>;
def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
let Predicates = [NotN64, HasStdEnc] in {
def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>;
def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>;
}
def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>,
Requires<[NotN64, HasStdEnc]>;
def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>;
def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>;
}
/// Jump and Branch Instructions

96
lib/Target/Mips/MipsInstrInfo.td
View File

@ -435,58 +435,36 @@ multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> {
// Load/Store Left/Right
let canFoldAsLoad = 1 in
class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
RegisterClass RC, Operand MemOpnd> :
FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
!strconcat(instr_asm, "\t$rt, $addr"),
[(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
Operand MemOpnd> :
InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
!strconcat(opstr, "\t$rt, $addr"),
[(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem";
string Constraints = "$src = $rt";
}
class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
!strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
IIStore>;
class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
Operand MemOpnd>:
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem";
}
// 32-bit load left/right.
multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
def #NAME# : LoadLeftRight<opstr, OpNode, RC, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 64-bit load left/right.
multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
def #NAME# : StoreLeftRight<opstr, OpNode, RC, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 32-bit store left/right.
multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 64-bit store left/right.
multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@ -736,15 +714,17 @@ multiclass AtomicCmpSwap32<PatFrag Op> {
}
}
class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
!strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
class LLBase<string opstr, RegisterClass RC, Operand Mem> :
InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
[], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem";
let mayLoad = 1;
}
class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
!strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
class SCBase<string opstr, RegisterClass RC, Operand Mem> :
InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr),
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
let Constraints = "$rt = $dst";
}
@ -850,10 +830,10 @@ defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>;
defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>;
/// load/store left/right
defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
let hasSideEffects = 1 in
def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
@ -867,18 +847,14 @@ def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
}
/// Load-linked, Store-conditional
def LL : LLBase<0x30, "ll", CPURegs, mem>,
Requires<[NotN64, HasStdEnc]>;
def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let Predicates = [NotN64, HasStdEnc] in {
def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>;
def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>;
}
def SC : SCBase<0x38, "sc", CPURegs, mem>,
Requires<[NotN64, HasStdEnc]>;
def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>;
def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>;
}
/// Jump and Branch Instructions