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Remove the CAND/COR/CXOR custom ISD nodes and their select code.

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These nodes are no longer needed because the peephole pass can fold
CMOV+AND into ANDCC etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-08-18 21:49:50 +00:00
parent 35fc62bf70
commit 0a8f898000
3 changed files with 0 additions and 174 deletions
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120
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -239,7 +239,6 @@ private:
/// SelectCMOVOp - Select CMOV instructions for ARM.
SDNode *SelectCMOVOp(SDNode *N);
SDNode *SelectConditionalOp(SDNode *N);
SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag);
@ -2363,121 +2362,6 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
}
SDNode *ARMDAGToDAGISel::SelectConditionalOp(SDNode *N) {
SDValue FalseVal = N->getOperand(0);
SDValue TrueVal = N->getOperand(1);
ARMCC::CondCodes CCVal =
(ARMCC::CondCodes)cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
SDValue CCR = N->getOperand(3);
assert(CCR.getOpcode() == ISD::Register);
SDValue InFlag = N->getOperand(4);
SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue CPTmp0;
SDValue CPTmp1;
if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::t2ANDCCrs; break;
case ARMISD::COR: Opc = ARM::t2ORRCCrs; break;
case ARMISD::CXOR: Opc = ARM::t2EORCCrs; break;
}
SDValue Ops[] = {
FalseVal, FalseVal, CPTmp0, CPTmp1, CC, CCR, Reg0, InFlag
};
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 8);
}
ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
if (T) {
unsigned TrueImm = T->getZExtValue();
if (is_t2_so_imm(TrueImm)) {
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::t2ANDCCri; break;
case ARMISD::COR: Opc = ARM::t2ORRCCri; break;
case ARMISD::CXOR: Opc = ARM::t2EORCCri; break;
}
SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
SDValue Ops[] = { FalseVal, FalseVal, True, CC, CCR, Reg0, InFlag };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
}
}
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::t2ANDCCrr; break;
case ARMISD::COR: Opc = ARM::t2ORRCCrr; break;
case ARMISD::CXOR: Opc = ARM::t2EORCCrr; break;
}
SDValue Ops[] = { FalseVal, FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
}
SDValue CPTmp0;
SDValue CPTmp1;
SDValue CPTmp2;
if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::ANDCCrsi; break;
case ARMISD::COR: Opc = ARM::ORRCCrsi; break;
case ARMISD::CXOR: Opc = ARM::EORCCrsi; break;
}
SDValue Ops[] = {
FalseVal, FalseVal, CPTmp0, CPTmp2, CC, CCR, Reg0, InFlag
};
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 8);
}
if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::ANDCCrsr; break;
case ARMISD::COR: Opc = ARM::ORRCCrsr; break;
case ARMISD::CXOR: Opc = ARM::EORCCrsr; break;
}
SDValue Ops[] = {
FalseVal, FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, Reg0, InFlag
};
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 9);
}
ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
if (T) {
unsigned TrueImm = T->getZExtValue();
if (is_so_imm(TrueImm)) {
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::ANDCCri; break;
case ARMISD::COR: Opc = ARM::ORRCCri; break;
case ARMISD::CXOR: Opc = ARM::EORCCri; break;
}
SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
SDValue Ops[] = { FalseVal, FalseVal, True, CC, CCR, Reg0, InFlag };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
}
}
unsigned Opc;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ARMISD::CAND: Opc = ARM::ANDCCrr; break;
case ARMISD::COR: Opc = ARM::ORRCCrr; break;
case ARMISD::CXOR: Opc = ARM::EORCCrr; break;
}
SDValue Ops[] = { FalseVal, FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
}
/// Target-specific DAG combining for ISD::XOR.
/// Target-independent combining lowers SELECT_CC nodes of the form
/// select_cc setg[ge] X, 0, X, -X
@ -2805,10 +2689,6 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
}
case ARMISD::CMOV:
return SelectCMOVOp(N);
case ARMISD::CAND:
case ARMISD::COR:
case ARMISD::CXOR:
return SelectConditionalOp(N);
case ARMISD::VZIP: {
unsigned Opc = 0;
EVT VT = N->getValueType(0);

51
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -898,9 +898,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
case ARMISD::CMOV: return "ARMISD::CMOV";
case ARMISD::CAND: return "ARMISD::CAND";
case ARMISD::COR: return "ARMISD::COR";
case ARMISD::CXOR: return "ARMISD::CXOR";
case ARMISD::RBIT: return "ARMISD::RBIT";
@ -7371,41 +7368,6 @@ static SDValue PerformMULCombine(SDNode *N,
return SDValue();
}
static bool isCMOVWithZeroOrAllOnesLHS(SDValue N, bool AllOnes) {
return N.getOpcode() == ARMISD::CMOV && N.getNode()->hasOneUse() &&
isZeroOrAllOnes(N.getOperand(0), AllOnes);
}
/// formConditionalOp - Combine an operation with a conditional move operand
/// to form a conditional op. e.g. (or x, (cmov 0, y, cond)) => (or.cond x, y)
/// (and x, (cmov -1, y, cond)) => (and.cond, x, y)
static SDValue formConditionalOp(SDNode *N, SelectionDAG &DAG,
bool Commutable) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
bool isAND = N->getOpcode() == ISD::AND;
bool isCand = isCMOVWithZeroOrAllOnesLHS(N1, isAND);
if (!isCand && Commutable) {
isCand = isCMOVWithZeroOrAllOnesLHS(N0, isAND);
if (isCand)
std::swap(N0, N1);
}
if (!isCand)
return SDValue();
unsigned Opc = 0;
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected node");
case ISD::AND: Opc = ARMISD::CAND; break;
case ISD::OR: Opc = ARMISD::COR; break;
case ISD::XOR: Opc = ARMISD::CXOR; break;
}
return DAG.getNode(Opc, N->getDebugLoc(), N->getValueType(0), N0,
N1.getOperand(1), N1.getOperand(2), N1.getOperand(3),
N1.getOperand(4));
}
static SDValue PerformANDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *Subtarget) {
@ -7444,10 +7406,6 @@ static SDValue PerformANDCombine(SDNode *N,
SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
if (Result.getNode())
return Result;
// (and x, (cmov -1, y, cond)) => (and.cond x, y)
SDValue CAND = formConditionalOp(N, DAG, true);
if (CAND.getNode())
return CAND;
}
return SDValue();
@ -7491,13 +7449,8 @@ static SDValue PerformORCombine(SDNode *N,
SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
if (Result.getNode())
return Result;
// (or x, (cmov 0, y, cond)) => (or.cond x, y)
SDValue COR = formConditionalOp(N, DAG, true);
if (COR.getNode())
return COR;
}
// The code below optimizes (or (and X, Y), Z).
// The AND operand needs to have a single user to make these optimizations
// profitable.
@ -7663,10 +7616,6 @@ static SDValue PerformXORCombine(SDNode *N,
SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
if (Result.getNode())
return Result;
// (xor x, (cmov 0, y, cond)) => (xor.cond x, y)
SDValue CXOR = formConditionalOp(N, DAG, true);
if (CXOR.getNode())
return CXOR;
}
return SDValue();

3
lib/Target/ARM/ARMISelLowering.h
View File

@ -63,9 +63,6 @@ namespace llvm {
FMSTAT, // ARM fmstat instruction.
CMOV, // ARM conditional move instructions.
CAND, // ARM conditional and instructions.
COR, // ARM conditional or instructions.
CXOR, // ARM conditional xor instructions.
BCC_i64,