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Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63199 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -374,12 +374,9 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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/// larger then ValueVT then AssertOp can be used to specify whether the extra
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/// larger then ValueVT then AssertOp can be used to specify whether the extra
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/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
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/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
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/// (ISD::AssertSext).
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/// (ISD::AssertSext).
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static SDValue getCopyFromParts(SelectionDAG &DAG,
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static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts,
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const SDValue *Parts,
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unsigned NumParts, MVT PartVT, MVT ValueVT,
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unsigned NumParts,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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MVT PartVT,
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MVT ValueVT,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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assert(NumParts > 0 && "No parts to assemble!");
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assert(NumParts > 0 && "No parts to assemble!");
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue Val = Parts[0];
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SDValue Val = Parts[0];
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@ -587,8 +584,8 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
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unsigned RoundBits = RoundParts * PartBits;
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unsigned RoundBits = RoundParts * PartBits;
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unsigned OddParts = NumParts - RoundParts;
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unsigned OddParts = NumParts - RoundParts;
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SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
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SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
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DAG.getConstant(RoundBits,
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DAG.getConstant(RoundBits,
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TLI.getShiftAmountTy()));
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TLI.getShiftAmountTy()));
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getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
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getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
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if (TLI.isBigEndian())
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if (TLI.isBigEndian())
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// The odd parts were reversed by getCopyToParts - unreverse them.
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// The odd parts were reversed by getCopyToParts - unreverse them.
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