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Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but

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it sets the CPSR register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-08-29 03:02:11 +00:00
parent fedb34665a
commit 0b4aa7d11b
3 changed files with 7 additions and 0 deletions
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1
lib/Target/ARM/ARMISelLowering.cpp
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@ -609,6 +609,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
case ARMISD::AND: return "ARMISD::AND";
case ARMISD::CMP: return "ARMISD::CMP";
case ARMISD::CMPZ: return "ARMISD::CMPZ";
case ARMISD::CMPFP: return "ARMISD::CMPFP";

2
lib/Target/ARM/ARMISelLowering.h
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@ -47,6 +47,8 @@ namespace llvm {
PIC_ADD, // Add with a PC operand and a PIC label.
AND, // ARM "and" instruction that sets the 's' flag in CPSR.
CMP, // ARM compare instructions.
CMPZ, // ARM compare that sets only Z flag.
CMPFP, // ARM VFP compare instruction, sets FPSCR.

4
lib/Target/ARM/ARMInstrThumb2.td
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@ -1631,6 +1631,10 @@ defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
let Defs = [CPSR] in
defm t2ANDflag : T2I_bin_w_irs<0b0000, "and",
BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
let Constraints = "$src = $dst" in
def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
IIC_iUNAsi, "bfc", "\t$dst, $imm",