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Fix 11769.

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In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2012-01-17 09:13:19 +00:00
parent d3b588965d
commit 0b94b5f52b
2 changed files with 19 additions and 1 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6241,6 +6241,13 @@ bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
// If we are accessing the upper part of a YMM register
// then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
// EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
// because the legalization of N did not happen yet.
if (Idx >= NumElems/2 && VT.getSizeInBits() == 256)
return false;
// Skip one more bit_convert if necessary
if (V.getOpcode() == ISD::BITCAST)
V = V.getOperand(0);

13
test/CodeGen/X86/avx-shuffle.ll
View File

@ -60,7 +60,18 @@ entry:
define <16 x i16> @test7(<4 x i16> %a) nounwind {
; CHECK: test7
%b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK: ret
ret <16 x i16> %b
}
; CHECK: test8
define void @test8() {
entry:
%0 = load <16 x i64> addrspace(1)* null, align 128
%1 = shufflevector <16 x i64> <i64 undef, i64 undef, i64 0, i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i64> %0, <16 x i32> <i32 17, i32 18, i32 2, i32 undef, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 26>
%2 = shufflevector <16 x i64> %1, <16 x i64> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 30, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 22, i32 20, i32 15>
store <16 x i64> %2, <16 x i64> addrspace(1)* undef, align 128
; CHECK: ret
ret void
}