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Mips specific inline assembler constraint 'R'

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'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter 2013-03-04 21:33:15 +00:00
parent 75d0ad4215
commit 0b9675d631
2 changed files with 14 additions and 0 deletions
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5
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3880,6 +3880,8 @@ getConstraintType(const std::string &Constraint) const
case 'l':
case 'x':
return C_RegisterClass;
case 'R':
return C_Memory;
}
}
return TargetLowering::getConstraintType(Constraint);
@ -3928,6 +3930,9 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
if (isa<ConstantInt>(CallOperandVal))
weight = CW_Constant;
break;
case 'R':
weight = CW_Memory;
break;
}
return weight;
}

9
test/CodeGen/Mips/inlineasm_constraint.ll
View File

@ -51,5 +51,14 @@ entry:
; CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
; Now R Which takes the address of c
%c = alloca i32, align 4
store i32 -4469539, i32* %c, align 4
%8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1
; CHECK: #APP
; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}})
; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}})
; CHECK: #NO_APP
ret i32 0
}