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Ensure REG_SEQUENCE source operands are unique.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-05-11 00:04:31 +00:00
parent a8251fac10
commit 0bcccac504
1 changed files with 19 additions and 0 deletions
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19
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -1164,6 +1164,8 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
llvm_unreachable(0); llvm_unreachable(0);
} }
SmallSet<unsigned, 4> Seen;
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
unsigned SrcReg = MI->getOperand(i).getReg(); unsigned SrcReg = MI->getOperand(i).getReg();
if (MI->getOperand(i).getSubReg() || if (MI->getOperand(i).getSubReg() ||
@ -1171,6 +1173,23 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
llvm_unreachable(0); llvm_unreachable(0);
} }
if (!Seen.insert(SrcReg)) {
// REG_SEQUENCE cannot have duplicated operands. Add a copy.
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
unsigned NewReg = MRI->createVirtualRegister(RC);
bool Emitted =
TII->copyRegToReg(*MI->getParent(), MI, NewReg, SrcReg, RC, RC,
MI->getDebugLoc());
(void)Emitted;
assert(Emitted && "Unable to issue a copy instruction!\n");
MI->getOperand(i).setReg(NewReg);
MI->getOperand(i).setIsKill();
}
}
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
unsigned SrcReg = MI->getOperand(i).getReg();
unsigned SrcIdx = MI->getOperand(i+1).getImm(); unsigned SrcIdx = MI->getOperand(i+1).getImm();
UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI); UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI);
} }