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Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to

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getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108115 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-07-12 00:52:33 +00:00
parent 0a96144aac
commit 0bfd09201e
2 changed files with 3 additions and 2 deletions
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2
lib/CodeGen/VirtRegRewriter.cpp
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@ -1703,7 +1703,7 @@ bool LocalRewriter::InsertEmergencySpills(MachineInstr *MI) {
std::vector<unsigned> &EmSpills = VRM->getEmergencySpills(MI);
for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
unsigned PhysReg = EmSpills[i];
const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(PhysReg);
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg);
assert(RC && "Unable to determine register class!");
int SS = VRM->getEmergencySpillSlot(RC);
if (UsedSS.count(SS))

3
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1960,7 +1960,8 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
bool load) {
if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
return load ? X86::MOV64rm : X86::MOV64mr;
} else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
} else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass ||
RC == &X86::GR32_ADRegClass) {
return load ? X86::MOV32rm : X86::MOV32mr;
} else if (RC == &X86::GR16RegClass) {
return load ? X86::MOV16rm : X86::MOV16mr;