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Reformat a loop for basic hygeine. Self review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199788 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2527,17 +2527,17 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) {
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unsigned NumRegionInstrs) {
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const TargetMachine &TM = Context->MF->getTarget();
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const TargetMachine &TM = Context->MF->getTarget();
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const TargetLowering *TLI = TM.getTargetLowering();
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// Avoid setting up the register pressure tracker for small regions to save
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// Avoid setting up the register pressure tracker for small regions to save
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// compile time. As a rough heuristic, only track pressure when the number of
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// compile time. As a rough heuristic, only track pressure when the number of
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// schedulable instructions exceeds half the integer register file.
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// schedulable instructions exceeds half the integer register file.
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RegionPolicy.ShouldTrackPressure = true;
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RegionPolicy.ShouldTrackPressure = true;
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unsigned LegalIntVT = MVT::i32;
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for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
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for (; LegalIntVT > (unsigned)MVT::i1; --LegalIntVT) {
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MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
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if (TM.getTargetLowering()->isTypeLegal((MVT::SimpleValueType)LegalIntVT)) {
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if (TLI->isTypeLegal(LegalIntVT)) {
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unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
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unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
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TM.getTargetLowering()->getRegClassFor(
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TLI->getRegClassFor(LegalIntVT));
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(MVT::SimpleValueType)LegalIntVT));
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RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
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RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
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}
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}
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}
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}
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