mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Move GenericScheduler and PostGenericScheduler into a header.
These were not exposed previously because I didn't want out-of-tree targets to be too dependent on their internals. They can be reused for a very wide variety of processors with casual scheduling needs without exposing the classes by instead using hooks defined in MachineSchedPolicy (we can add more if needed). When targets are more aggressively tuned or want to provide custom heuristics, they can define their own MachineSchedStrategy. I tend to think this is better once you start customizing heuristics because you can copy over only what you need. I don't think that layering heuristics generally works well. However, Arch64 targets now want to reuse the Generic scheduling logic but also provide extensions. I don't see much harm in exposing the Generic scheduling classes with a major caveat: these scheduling strategies may change in the future without validating performance on less mainstream processors. If you want to be immune from changes, just define your own MachineSchedStrategy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
e5d8481310
commit
0c83424556
@ -739,6 +739,217 @@ public:
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#endif
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};
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/// Base class for GenericScheduler. This class maintains information about
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/// scheduling candidates based on TargetSchedModel making it easy to implement
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/// heuristics for either preRA or postRA scheduling.
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class GenericSchedulerBase : public MachineSchedStrategy {
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public:
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/// Represent the type of SchedCandidate found within a single queue.
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/// pickNodeBidirectional depends on these listed by decreasing priority.
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enum CandReason {
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NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
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ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
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TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
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#ifndef NDEBUG
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static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
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#endif
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/// Policy for scheduling the next instruction in the candidate's zone.
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struct CandPolicy {
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bool ReduceLatency;
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unsigned ReduceResIdx;
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unsigned DemandResIdx;
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CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
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};
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/// Status of an instruction's critical resource consumption.
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struct SchedResourceDelta {
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// Count critical resources in the scheduled region required by SU.
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unsigned CritResources;
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// Count critical resources from another region consumed by SU.
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unsigned DemandedResources;
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SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
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bool operator==(const SchedResourceDelta &RHS) const {
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return CritResources == RHS.CritResources
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&& DemandedResources == RHS.DemandedResources;
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}
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bool operator!=(const SchedResourceDelta &RHS) const {
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return !operator==(RHS);
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}
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};
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/// Store the state used by GenericScheduler heuristics, required for the
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/// lifetime of one invocation of pickNode().
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struct SchedCandidate {
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CandPolicy Policy;
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// The best SUnit candidate.
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SUnit *SU;
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// The reason for this candidate.
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CandReason Reason;
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// Set of reasons that apply to multiple candidates.
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uint32_t RepeatReasonSet;
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// Register pressure values for the best candidate.
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RegPressureDelta RPDelta;
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// Critical resource consumption of the best candidate.
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SchedResourceDelta ResDelta;
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SchedCandidate(const CandPolicy &policy)
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: Policy(policy), SU(nullptr), Reason(NoCand), RepeatReasonSet(0) {}
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bool isValid() const { return SU; }
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// Copy the status of another candidate without changing policy.
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void setBest(SchedCandidate &Best) {
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assert(Best.Reason != NoCand && "uninitialized Sched candidate");
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SU = Best.SU;
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Reason = Best.Reason;
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RPDelta = Best.RPDelta;
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ResDelta = Best.ResDelta;
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}
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bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
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void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
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void initResourceDelta(const ScheduleDAGMI *DAG,
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const TargetSchedModel *SchedModel);
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};
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protected:
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const MachineSchedContext *Context;
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const TargetSchedModel *SchedModel;
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const TargetRegisterInfo *TRI;
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SchedRemainder Rem;
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protected:
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GenericSchedulerBase(const MachineSchedContext *C):
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Context(C), SchedModel(nullptr), TRI(nullptr) {}
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void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
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SchedBoundary *OtherZone);
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#ifndef NDEBUG
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void traceCandidate(const SchedCandidate &Cand);
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#endif
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};
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/// GenericScheduler shrinks the unscheduled zone using heuristics to balance
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/// the schedule.
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class GenericScheduler : public GenericSchedulerBase {
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ScheduleDAGMILive *DAG;
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// State of the top and bottom scheduled instruction boundaries.
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SchedBoundary Top;
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SchedBoundary Bot;
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MachineSchedPolicy RegionPolicy;
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public:
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GenericScheduler(const MachineSchedContext *C):
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GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
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Bot(SchedBoundary::BotQID, "BotQ") {}
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void initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) override;
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bool shouldTrackPressure() const override {
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return RegionPolicy.ShouldTrackPressure;
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}
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void initialize(ScheduleDAGMI *dag) override;
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SUnit *pickNode(bool &IsTopNode) override;
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void schedNode(SUnit *SU, bool IsTopNode) override;
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void releaseTopNode(SUnit *SU) override {
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Top.releaseTopNode(SU);
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}
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void releaseBottomNode(SUnit *SU) override {
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Bot.releaseBottomNode(SU);
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}
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void registerRoots() override;
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protected:
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void checkAcyclicLatency();
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void tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone,
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const RegPressureTracker &RPTracker,
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RegPressureTracker &TempTracker);
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SUnit *pickNodeBidirectional(bool &IsTopNode);
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void pickNodeFromQueue(SchedBoundary &Zone,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Candidate);
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void reschedulePhysRegCopies(SUnit *SU, bool isTop);
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};
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/// PostGenericScheduler - Interface to the scheduling algorithm used by
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/// ScheduleDAGMI.
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///
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/// Callbacks from ScheduleDAGMI:
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/// initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...
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class PostGenericScheduler : public GenericSchedulerBase {
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ScheduleDAGMI *DAG;
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SchedBoundary Top;
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SmallVector<SUnit*, 8> BotRoots;
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public:
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PostGenericScheduler(const MachineSchedContext *C):
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GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ") {}
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virtual ~PostGenericScheduler() {}
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void initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) override {
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/* no configurable policy */
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};
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/// PostRA scheduling does not track pressure.
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bool shouldTrackPressure() const override { return false; }
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void initialize(ScheduleDAGMI *Dag) override;
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void registerRoots() override;
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SUnit *pickNode(bool &IsTopNode) override;
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void scheduleTree(unsigned SubtreeID) override {
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llvm_unreachable("PostRA scheduler does not support subtree analysis.");
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}
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void schedNode(SUnit *SU, bool IsTopNode) override;
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void releaseTopNode(SUnit *SU) override {
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Top.releaseTopNode(SU);
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}
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// Only called for roots.
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void releaseBottomNode(SUnit *SU) override {
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BotRoots.push_back(SU);
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}
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protected:
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void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
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void pickNodeFromQueue(SchedCandidate &Cand);
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};
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} // namespace llvm
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#endif
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@ -2090,111 +2090,6 @@ void SchedBoundary::dumpScheduledState() {
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// GenericScheduler - Generic implementation of MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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namespace {
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/// Base class for GenericScheduler. This class maintains information about
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/// scheduling candidates based on TargetSchedModel making it easy to implement
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/// heuristics for either preRA or postRA scheduling.
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class GenericSchedulerBase : public MachineSchedStrategy {
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public:
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/// Represent the type of SchedCandidate found within a single queue.
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/// pickNodeBidirectional depends on these listed by decreasing priority.
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enum CandReason {
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NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
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ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
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TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
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#ifndef NDEBUG
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static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
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#endif
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/// Policy for scheduling the next instruction in the candidate's zone.
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struct CandPolicy {
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bool ReduceLatency;
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unsigned ReduceResIdx;
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unsigned DemandResIdx;
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CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
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};
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/// Status of an instruction's critical resource consumption.
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struct SchedResourceDelta {
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// Count critical resources in the scheduled region required by SU.
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unsigned CritResources;
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// Count critical resources from another region consumed by SU.
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unsigned DemandedResources;
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SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
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bool operator==(const SchedResourceDelta &RHS) const {
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return CritResources == RHS.CritResources
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&& DemandedResources == RHS.DemandedResources;
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}
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bool operator!=(const SchedResourceDelta &RHS) const {
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return !operator==(RHS);
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}
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};
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/// Store the state used by GenericScheduler heuristics, required for the
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/// lifetime of one invocation of pickNode().
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struct SchedCandidate {
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CandPolicy Policy;
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// The best SUnit candidate.
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SUnit *SU;
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// The reason for this candidate.
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CandReason Reason;
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// Set of reasons that apply to multiple candidates.
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uint32_t RepeatReasonSet;
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// Register pressure values for the best candidate.
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RegPressureDelta RPDelta;
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// Critical resource consumption of the best candidate.
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SchedResourceDelta ResDelta;
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SchedCandidate(const CandPolicy &policy)
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: Policy(policy), SU(nullptr), Reason(NoCand), RepeatReasonSet(0) {}
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bool isValid() const { return SU; }
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// Copy the status of another candidate without changing policy.
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void setBest(SchedCandidate &Best) {
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assert(Best.Reason != NoCand && "uninitialized Sched candidate");
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SU = Best.SU;
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Reason = Best.Reason;
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RPDelta = Best.RPDelta;
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ResDelta = Best.ResDelta;
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}
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bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
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void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
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void initResourceDelta(const ScheduleDAGMI *DAG,
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const TargetSchedModel *SchedModel);
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};
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protected:
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const MachineSchedContext *Context;
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const TargetSchedModel *SchedModel;
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const TargetRegisterInfo *TRI;
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SchedRemainder Rem;
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protected:
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GenericSchedulerBase(const MachineSchedContext *C):
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Context(C), SchedModel(nullptr), TRI(nullptr) {}
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void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
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SchedBoundary *OtherZone);
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#ifndef NDEBUG
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void traceCandidate(const SchedCandidate &Cand);
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#endif
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};
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} // namespace
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void GenericSchedulerBase::SchedCandidate::
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initResourceDelta(const ScheduleDAGMI *DAG,
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const TargetSchedModel *SchedModel) {
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@ -2430,65 +2325,6 @@ static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand,
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<< GenericSchedulerBase::getReasonStr(Cand.Reason) << '\n');
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}
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namespace {
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/// GenericScheduler shrinks the unscheduled zone using heuristics to balance
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/// the schedule.
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class GenericScheduler : public GenericSchedulerBase {
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ScheduleDAGMILive *DAG;
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// State of the top and bottom scheduled instruction boundaries.
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SchedBoundary Top;
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SchedBoundary Bot;
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MachineSchedPolicy RegionPolicy;
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public:
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GenericScheduler(const MachineSchedContext *C):
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GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
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Bot(SchedBoundary::BotQID, "BotQ") {}
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void initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) override;
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bool shouldTrackPressure() const override {
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return RegionPolicy.ShouldTrackPressure;
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}
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void initialize(ScheduleDAGMI *dag) override;
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SUnit *pickNode(bool &IsTopNode) override;
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void schedNode(SUnit *SU, bool IsTopNode) override;
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void releaseTopNode(SUnit *SU) override {
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Top.releaseTopNode(SU);
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}
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void releaseBottomNode(SUnit *SU) override {
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Bot.releaseBottomNode(SU);
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}
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void registerRoots() override;
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protected:
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void checkAcyclicLatency();
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void tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone,
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const RegPressureTracker &RPTracker,
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RegPressureTracker &TempTracker);
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SUnit *pickNodeBidirectional(bool &IsTopNode);
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void pickNodeFromQueue(SchedBoundary &Zone,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Candidate);
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void reschedulePhysRegCopies(SUnit *SU, bool isTop);
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};
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} // namespace
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void GenericScheduler::initialize(ScheduleDAGMI *dag) {
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assert(dag->hasVRegLiveness() &&
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"(PreRA)GenericScheduler needs vreg liveness");
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@ -3023,75 +2859,25 @@ GenericSchedRegistry("converge", "Standard converging scheduler.",
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// PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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namespace {
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/// PostGenericScheduler - Interface to the scheduling algorithm used by
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/// ScheduleDAGMI.
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///
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/// Callbacks from ScheduleDAGMI:
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/// initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...
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class PostGenericScheduler : public GenericSchedulerBase {
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ScheduleDAGMI *DAG;
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SchedBoundary Top;
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SmallVector<SUnit*, 8> BotRoots;
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public:
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PostGenericScheduler(const MachineSchedContext *C):
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GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ") {}
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void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
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DAG = Dag;
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SchedModel = DAG->getSchedModel();
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TRI = DAG->TRI;
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virtual ~PostGenericScheduler() {}
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Rem.init(DAG, SchedModel);
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Top.init(DAG, SchedModel, &Rem);
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BotRoots.clear();
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void initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) override {
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/* no configurable policy */
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};
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/// PostRA scheduling does not track pressure.
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bool shouldTrackPressure() const override { return false; }
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void initialize(ScheduleDAGMI *Dag) override {
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DAG = Dag;
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SchedModel = DAG->getSchedModel();
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TRI = DAG->TRI;
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Rem.init(DAG, SchedModel);
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Top.init(DAG, SchedModel, &Rem);
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BotRoots.clear();
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// Initialize the HazardRecognizers. If itineraries don't exist, are empty,
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// or are disabled, then these HazardRecs will be disabled.
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const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
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const TargetMachine &TM = DAG->MF.getTarget();
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if (!Top.HazardRec) {
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Top.HazardRec =
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TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
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}
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// Initialize the HazardRecognizers. If itineraries don't exist, are empty,
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// or are disabled, then these HazardRecs will be disabled.
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const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
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const TargetMachine &TM = DAG->MF.getTarget();
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if (!Top.HazardRec) {
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Top.HazardRec =
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TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
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}
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}
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void registerRoots() override;
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SUnit *pickNode(bool &IsTopNode) override;
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void scheduleTree(unsigned SubtreeID) override {
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llvm_unreachable("PostRA scheduler does not support subtree analysis.");
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}
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void schedNode(SUnit *SU, bool IsTopNode) override;
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void releaseTopNode(SUnit *SU) override {
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Top.releaseTopNode(SU);
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}
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// Only called for roots.
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void releaseBottomNode(SUnit *SU) override {
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BotRoots.push_back(SU);
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}
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protected:
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void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
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void pickNodeFromQueue(SchedCandidate &Cand);
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};
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} // namespace
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void PostGenericScheduler::registerRoots() {
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Rem.CriticalPath = DAG->ExitSU.getDepth();
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