From 0c922879854f5a6ee60283b99c68089f76f94778 Mon Sep 17 00:00:00 2001 From: Vincent Lejeune Date: Mon, 3 Jun 2013 15:56:12 +0000 Subject: [PATCH] R600: 3 op instructions have no write bit but the result are store in PV git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/R600Packetizer.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp index 033c0b410c8..da614c73e1c 100644 --- a/lib/Target/R600/R600Packetizer.cpp +++ b/lib/Target/R600/R600Packetizer.cpp @@ -80,9 +80,7 @@ private: if (TII->isTransOnly(BI)) continue; int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE); - if (OperandIdx < 0) - continue; - if (BI->getOperand(OperandIdx).getImm() == 0) + if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0) continue; unsigned Dst = BI->getOperand(0).getReg(); if (BI->getOpcode() == AMDGPU::DOT4_r600 ||