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shl is always zero extending, so always use a zero extending shift right.
This latent bug was exposed by recent changes, and is tested as: llvm/test/Regression/Transforms/InstCombine/2004-09-28-BadShiftAndSetCC.llx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16546 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1506,7 +1506,7 @@ Instruction *InstCombiner::visitSetCondInst(BinaryOperator &I) {
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// rights, as they sign-extend.
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if (ShAmt) {
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bool CanFold = Shift->getOpcode() != Instruction::Shr ||
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Shift->getType()->isUnsigned();
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Shift->getType()->isUnsigned();
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if (!CanFold) {
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// To test for the bad case of the signed shr, see if any
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// of the bits shifted in could be tested after the mask.
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@ -1519,9 +1519,11 @@ Instruction *InstCombiner::visitSetCondInst(BinaryOperator &I) {
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}
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if (CanFold) {
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unsigned ShiftOp = Shift->getOpcode() == Instruction::Shl
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? Instruction::Shr : Instruction::Shl;
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Constant *NewCst = ConstantExpr::get(ShiftOp, CI, ShAmt);
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Constant *NewCst;
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if (Shift->getOpcode() == Instruction::Shl)
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NewCst = ConstantExpr::getUShr(CI, ShAmt);
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else
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NewCst = ConstantExpr::getShl(CI, ShAmt);
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// Check to see if we are shifting out any of the bits being
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// compared.
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@ -1535,7 +1537,12 @@ Instruction *InstCombiner::visitSetCondInst(BinaryOperator &I) {
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return ReplaceInstUsesWith(I, ConstantBool::True);
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} else {
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I.setOperand(1, NewCst);
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LHSI->setOperand(1, ConstantExpr::get(ShiftOp, AndCST,ShAmt));
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Constant *NewAndCST;
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if (Shift->getOpcode() == Instruction::Shl)
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NewAndCST = ConstantExpr::getUShr(AndCST, ShAmt);
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else
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NewAndCST = ConstantExpr::getShl(AndCST, ShAmt);
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LHSI->setOperand(1, NewAndCST);
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LHSI->setOperand(0, Shift->getOperand(0));
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WorkList.push_back(Shift); // Shift is dead.
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AddUsesToWorkList(I);
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