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https://github.com/c64scene-ar/llvm-6502.git
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Fix FP_TO_INT**_IN_MEM lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25368 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
7c898553b6
commit
0cc3945efe
@ -642,64 +642,6 @@ SDOperand X86DAGToDAGISel::Select(SDOperand N) {
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return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result);
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break;
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}
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case X86ISD::FP_TO_INT16_IN_MEM:
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case X86ISD::FP_TO_INT32_IN_MEM:
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case X86ISD::FP_TO_INT64_IN_MEM: {
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assert(N.getOperand(1).getValueType() == MVT::f64);
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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MachineFunction &MF = CurDAG->getMachineFunction();
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int CWFI = MF.getFrameInfo()->CreateStackObject(2, 2);
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SDOperand CWSlot = CurDAG->getFrameIndex(CWFI, MVT::i32);
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SDOperand Base, Scale, Index, Disp;
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(void)SelectAddr(CWSlot, Base, Scale, Index, Disp);
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SDOperand Chain = N.getOperand(0);
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// Save the control word.
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Chain = CurDAG->getTargetNode(X86::FNSTCW16m, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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// Load the old value of the high byte of the control word.
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SDOperand OldCW =
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CurDAG->getTargetNode(X86::MOV16rm, MVT::i16, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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Chain = OldCW.getValue(1);
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// Set the high part to be round to zero...
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Chain = CurDAG->getTargetNode(X86::MOV16mi, MVT::Other,
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Base, Scale, Index, Disp,
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CurDAG->getConstant(0xC7F, MVT::i16),
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Chain);
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// Reload the modified control word now...
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Chain = CurDAG->getTargetNode(X86::FLDCW16m, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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// Restore the memory image of control word to original value
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Chain = CurDAG->getTargetNode(X86::MOV16mr, MVT::Other,
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Base, Scale, Index, Disp, OldCW, Chain);
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switch (Opcode) {
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default: assert(0 && "Unknown FP_TO_INT*_IN_MEM");
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case X86ISD::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
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case X86ISD::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
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case X86ISD::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
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}
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SDOperand N1 = Select(N.getOperand(1));
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SDOperand Base2, Scale2, Index2, Disp2;
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(void)SelectAddr(N.getOperand(2), Base2, Scale2, Index2, Disp2);
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Chain = CurDAG->getTargetNode(Opc, MVT::Other,
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Base2, Scale2, Index2, Disp2, N1, Chain);
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// Reload the modified control word now...
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CodeGenMap[N] =
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Chain = CurDAG->getTargetNode(X86::FLDCW16m, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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return Chain;
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}
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}
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return SelectCode(N);
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@ -13,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86TargetMachine.h"
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#include "llvm/CallingConv.h"
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@ -1261,54 +1262,117 @@ static bool hasFPCMov(unsigned X86CC) {
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MachineBasicBlock *
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X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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assert((MI->getOpcode() == X86::CMOV_FR32 ||
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MI->getOpcode() == X86::CMOV_FR64) &&
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"Unexpected instr type to insert");
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case X86::CMOV_FR32:
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case X86::CMOV_FR64: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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// to set, the condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
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BuildMI(BB, Opc, 1).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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// to set, the condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
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BuildMI(BB, Opc, 1).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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delete MI; // The pseudo instruction is gone now.
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return BB;
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case X86::FP_TO_INT16_IN_MEM:
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case X86::FP_TO_INT32_IN_MEM:
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case X86::FP_TO_INT64_IN_MEM: {
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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MachineFunction *F = BB->getParent();
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int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
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addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
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// Load the old value of the high byte of the control word...
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unsigned OldCW =
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F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
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addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
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// Set the high part to be round to zero...
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addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
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// Reload the modified control word now...
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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// Restore the memory image of control word to original value
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addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
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// Get the X86 opcode to use.
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unsigned Opc;
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switch (MI->getOpcode()) {
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case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
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case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
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case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
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}
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X86AddressMode AM;
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MachineOperand &Op = MI->getOperand(0);
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if (Op.isRegister()) {
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = Op.getReg();
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} else {
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AM.BaseType = X86AddressMode::FrameIndexBase;
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AM.Base.FrameIndex = Op.getFrameIndex();
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}
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Op = MI->getOperand(1);
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if (Op.isImmediate())
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AM.Scale = Op.getImmedValue();
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Op = MI->getOperand(2);
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if (Op.isImmediate())
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AM.IndexReg = Op.getImmedValue();
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Op = MI->getOperand(3);
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if (Op.isGlobalAddress()) {
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AM.GV = Op.getGlobal();
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} else {
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AM.Disp = Op.getImmedValue();
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}
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addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
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// Reload the original control word now.
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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}
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}
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@ -52,6 +52,7 @@ def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
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SDTCisVT<2, OtherVT>]>;
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def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
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@ -102,6 +103,12 @@ def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain]>;
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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[SDNPHasChain]>;
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
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[SDNPHasChain, SDNPInFlag]>;
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@ -401,16 +408,32 @@ def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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def CMOV_FR32 : I<0, Pseudo,
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(ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
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"#CMOV PSEUDO!",
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"#CMOV_FR32 PSEUDO!",
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[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
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STATUS))]>;
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def CMOV_FR64 : I<0, Pseudo,
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(ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
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"#CMOV PSEUDO!",
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"#CMOV_FR64 PSEUDO!",
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[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
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STATUS))]>;
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}
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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def FP_TO_INT16_IN_MEM : I<0, Pseudo,
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(ops i16mem:$dst, RFP:$src),
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"#FP_TO_INT16_IN_MEM PSEUDO!",
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[(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
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def FP_TO_INT32_IN_MEM : I<0, Pseudo,
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(ops i32mem:$dst, RFP:$src),
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"#FP_TO_INT32_IN_MEM PSEUDO!",
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[(X86fp_to_i32mem RFP:$src, addr:$dst)]>;
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def FP_TO_INT64_IN_MEM : I<0, Pseudo,
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(ops i64mem:$dst, RFP:$src),
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"#FP_TO_INT64_IN_MEM PSEUDO!",
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[(X86fp_to_i64mem RFP:$src, addr:$dst)]>;
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}
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let isTerminator = 1 in
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let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
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def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
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