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AVX-512: MUL operation lowering for v8i64

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193083 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2013-10-21 13:27:34 +00:00
parent 348da8d6b5
commit 0cfca3d7ac
2 changed files with 14 additions and 4 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -12402,8 +12402,8 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
}
assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
"Only know how to lower V2I64/V4I64 multiply");
assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
"Only know how to lower V2I64/V4I64/V8I64 multiply");
// Ahi = psrlqi(a, 32);
// Bhi = psrlqi(b, 32);
@ -12422,7 +12422,8 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
// Bit cast to 32-bit vectors for MULUDQ
EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
(VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);

11
test/CodeGen/X86/avx512-arith.ll
View File

@ -74,6 +74,15 @@ entry:
ret <16 x float> %sub.i
}
; CHECK-LABEL: imulq512
; CHECK: vpmuludq
; CHECK: vpmuludq
; CHECK: ret
define <8 x i64> @imulq512(<8 x i64> %y, <8 x i64> %x) {
%z = mul <8 x i64>%x, %y
ret <8 x i64>%z
}
; CHECK-LABEL: mulpd512
; CHECK: vmulpd
; CHECK: ret
@ -259,4 +268,4 @@ entry:
%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
%d = and <8 x i64> %p1, %c
ret <8 x i64>%d
}
}