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Move code around to prepare for moving some of the logic together to another function

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113267 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-09-07 20:20:27 +00:00
parent c88c11d607
commit 0d1340b181
1 changed files with 3 additions and 3 deletions
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6
lib/Target/X86/X86ISelLowering.cpp
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@ -5271,9 +5271,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
if (isZeroShuffle(SVOp))
return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
// FIXME: this is somehow handled during isel by MMX pattern fragments. Remove
// the check or come up with another solution when all MMX move to intrinsics,
// but don't allow this to be considered legal, we don't want vector_shuffle
@ -5281,6 +5278,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
if (isMMX && SVOp->isSplat())
return Op;
if (isZeroShuffle(SVOp))
return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
// Promote splats to v4f32.
if (SVOp->isSplat())
return PromoteSplat(SVOp, DAG);