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Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-09-20 21:38:18 +00:00
parent 1daa5bea58
commit 0d18174f0f
2 changed files with 43 additions and 9 deletions
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8
lib/Target/ARM/ARM.td
View File

@ -108,7 +108,7 @@ def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
[HasV5TEOps]>;
def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
"Support ARM v6t2 instructions",
[HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
[HasV6Ops, FeatureThumb2]>;
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
"Support ARM v7 instructions",
[HasV6T2Ops]>;
@ -188,9 +188,11 @@ def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
FeatureDB]>;
// V6T2 Processors.
def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>;
def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
FeatureDSPThumb2]>;
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
FeatureHasSlowFPVMLx,
FeatureDSPThumb2]>;
// V7a Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,

44
test/CodeGen/ARM/mulhi.ll
View File

@ -1,9 +1,16 @@
; RUN: llc < %s -march=arm -mattr=+v6
; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep smmul | count 1
; RUN: llc < %s -march=arm | grep umull | count 1
; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -check-prefix=V6
; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=V4
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
define i32 @smulhi(i32 %x, i32 %y) {
define i32 @smulhi(i32 %x, i32 %y) nounwind {
; V6: smulhi:
; V6: smmul
; V4: smulhi:
; V4: smull
; M3: smulhi:
; M3: smull
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
%tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
@ -12,7 +19,15 @@ define i32 @smulhi(i32 %x, i32 %y) {
ret i32 %tmp3.upgrd.1
}
define i32 @umulhi(i32 %x, i32 %y) {
define i32 @umulhi(i32 %x, i32 %y) nounwind {
; V6: umulhi:
; V6: umull
; V4: umulhi:
; V4: umull
; M3: umulhi:
; M3: umull
%tmp = zext i32 %x to i64 ; <i64> [#uses=1]
%tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
@ -20,3 +35,20 @@ define i32 @umulhi(i32 %x, i32 %y) {
%tmp3.upgrd.2 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
ret i32 %tmp3.upgrd.2
}
; rdar://r10152911
define i32 @t3(i32 %a) nounwind {
; V6: t3:
; V6: smmla
; V4: t3:
; V4: smull
; M3: t3:
; M3-NOT: smmla
; M3: smull
entry:
%tmp1 = mul nsw i32 %a, 3
%tmp2 = sdiv i32 %tmp1, 23
ret i32 %tmp2
}