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Add Cortex-A57 support

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bernard Ogden 2013-10-14 13:17:07 +00:00
parent 7220572e74
commit 0d1e2aebe6
3 changed files with 23 additions and 1 deletions
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9
lib/Target/ARM/ARM.td
View File

@ -203,6 +203,12 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
FeatureTrustZone, FeatureT2XtPk, FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>; FeatureCrypto]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors",
[FeatureMP, FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>;
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors", "Cortex-R5 ARM processors",
[FeatureSlowFPBrcc, [FeatureSlowFPBrcc,
@ -326,6 +332,9 @@ def : ProcessorModel<"swift", SwiftModel,
def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass, def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
FeatureDB, FeatureFPARMv8, FeatureDB, FeatureFPARMv8,
FeatureNEON, FeatureDSPThumb2]>; FeatureNEON, FeatureDSPThumb2]>;
def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
FeatureDB, FeatureFPARMv8,
FeatureNEON, FeatureDSPThumb2]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description // Register File Description

2
lib/Target/ARM/ARMSubtarget.h
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@ -31,7 +31,7 @@ class TargetOptions;
class ARMSubtarget : public ARMGenSubtargetInfo { class ARMSubtarget : public ARMGenSubtargetInfo {
protected: protected:
enum ARMProcFamilyEnum { enum ARMProcFamilyEnum {
Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53, CortexA57
}; };
enum ARMProcClassEnum { enum ARMProcClassEnum {
None, AClass, RClass, MClass None, AClass, RClass, MClass

13
test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
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@ -14,6 +14,7 @@
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
; This tests that MC/asm header conversion is smooth and that build attributes are correct ; This tests that MC/asm header conversion is smooth and that build attributes are correct
; ;
@ -147,6 +148,18 @@
; CORTEX-A53: .eabi_attribute 25, 1 ; CORTEX-A53: .eabi_attribute 25, 1
; CORTEX-A53: .eabi_attribute 44, 2 ; CORTEX-A53: .eabi_attribute 44, 2
; CORTEX-A57: .cpu cortex-a57
; CORTEX-A57: .eabi_attribute 6, 14
; CORTEX-A57: .eabi_attribute 7, 65
; CORTEX-A57: .eabi_attribute 8, 1
; CORTEX-A57: .eabi_attribute 9, 2
; CORTEX-A57: .fpu crypto-neon-fp-armv8
; CORTEX-A57: .eabi_attribute 10, 7
; CORTEX-A57: .eabi_attribute 12, 3
; CORTEX-A57: .eabi_attribute 24, 1
; CORTEX-A57: .eabi_attribute 25, 1
; CORTEX-A57: .eabi_attribute 44, 2
define i32 @f(i64 %z) { define i32 @f(i64 %z) {
ret i32 0 ret i32 0
} }