mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-05 17:39:16 +00:00
Refactor address mode handling into a single struct (ala x86), this
should give allow a wider range of addressing modes. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119856 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
6571101cb7
commit
0d58122e12
@ -53,6 +53,29 @@ DisableARMFastISel("disable-arm-fast-isel",
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cl::init(false), cl::Hidden);
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namespace {
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// All possible address modes, plus some.
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typedef struct Address {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int Offset;
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unsigned Scale;
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unsigned PlusReg;
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// Innocuous defaults for our address.
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Address()
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: BaseType(RegBase), Offset(0), Scale(0), PlusReg(0) {
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Base.Reg = 0;
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}
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} Address;
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class ARMFastISel : public FastISel {
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@ -138,10 +161,10 @@ class ARMFastISel : public FastISel {
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private:
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bool isTypeLegal(const Type *Ty, MVT &VT);
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bool isLoadTypeLegal(const Type *Ty, MVT &VT);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
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bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
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void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
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bool ARMComputeAddress(const Value *Obj, Address &Addr);
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void ARMSimplifyAddress(Address &Addr, EVT VT);
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unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
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unsigned ARMMaterializeInt(const Constant *C, EVT VT);
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unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
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@ -581,8 +604,7 @@ bool ARMFastISel::isLoadTypeLegal(const Type *Ty, MVT &VT) {
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}
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// Computes the Reg+Offset to get to an object.
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bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
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int &Offset) {
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bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
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// Some boilerplate from the X86 FastISel.
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const User *U = NULL;
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unsigned Opcode = Instruction::UserOp1;
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@ -611,24 +633,24 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
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break;
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case Instruction::BitCast: {
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// Look through bitcasts.
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return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
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return ARMComputeAddress(U->getOperand(0), Addr);
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}
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case Instruction::IntToPtr: {
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
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return ARMComputeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::PtrToInt: {
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
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return ARMComputeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::GetElementPtr: {
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int SavedOffset = Offset;
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unsigned SavedBase = Base;
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int TmpOffset = Offset;
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int SavedOffset = Addr.Offset;
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unsigned SavedBase = Addr.Base.Reg;
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int TmpOffset = Addr.Offset;
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// Iterate through the GEP folding the constants into offsets where
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// we can.
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@ -664,12 +686,12 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
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}
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// Try to grab the base operand now.
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Offset = TmpOffset;
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if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
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Addr.Offset = TmpOffset;
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if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
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// We failed, restore everything and try the other options.
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Offset = SavedOffset;
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Base = SavedBase;
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Addr.Offset = SavedOffset;
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Addr.Base.Reg = SavedBase;
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unsupported_gep:
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break;
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@ -680,7 +702,7 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
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if (Reg == 0) return false;
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Base = Reg;
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Addr.Base.Reg = Reg;
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return true;
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}
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}
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@ -691,16 +713,16 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
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unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
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if (Tmp == 0) return false;
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Base = Tmp;
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Addr.Base.Reg = Tmp;
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return true;
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}
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// Try to get this in a register if nothing else has worked.
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if (Base == 0) Base = getRegForValue(Obj);
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return Base != 0;
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if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
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return Addr.Base.Reg != 0;
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}
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void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
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void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
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assert(VT.isSimple() && "Non-simple types are invalid here!");
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@ -713,12 +735,12 @@ void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
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case MVT::i16:
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case MVT::i32:
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// Integer loads/stores handle 12-bit offsets.
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needsLowering = ((Offset & 0xfff) != Offset);
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needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
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break;
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case MVT::f32:
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case MVT::f64:
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// Floating point operands handle 8-bit offsets.
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needsLowering = ((Offset & 0xff) != Offset);
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needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
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break;
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}
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@ -734,21 +756,21 @@ void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
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if (!isThumb)
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emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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BaseReg, Base, Offset, Pred, PredReg,
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BaseReg, Addr.Base.Reg, Addr.Offset,
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Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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else {
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assert(AFI->isThumb2Function());
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emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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BaseReg, Base, Offset, Pred, PredReg,
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BaseReg, Addr.Base.Reg, Addr.Offset, Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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}
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Offset = 0;
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Base = BaseReg;
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Addr.Offset = 0;
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Addr.Base.Reg = BaseReg;
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}
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}
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bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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unsigned Base, int Offset) {
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bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
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assert(VT.isSimple() && "Non-simple types are invalid here!");
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unsigned Opc;
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@ -784,22 +806,22 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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ResultReg = createResultReg(RC);
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ARMSimplifyRegOffset(Base, Offset, VT);
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ARMSimplifyAddress(Addr, VT);
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// addrmode5 output depends on the selection dag addressing dividing the
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// offset by 4 that it then later multiplies. Do this here as well.
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if (isFloat)
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Offset /= 4;
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Addr.Offset /= 4;
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// LDRH needs an additional operand.
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if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base).addReg(0).addImm(Offset));
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.addReg(Addr.Base.Reg).addReg(0).addImm(Addr.Offset));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base).addImm(Offset));
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.addReg(Addr.Base.Reg).addImm(Addr.Offset));
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return true;
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}
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@ -810,22 +832,20 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
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return false;
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// Our register and offset with innocuous defaults.
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unsigned Base = 0;
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int Offset = 0;
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Address Addr;
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// See if we can handle this as Reg + Offset
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if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
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if (!ARMComputeAddress(I->getOperand(0), Addr))
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return false;
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unsigned ResultReg;
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if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
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if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
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unsigned Base, int Offset) {
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bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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unsigned StrOpc;
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bool isFloat = false;
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bool needReg0Op = false;
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@ -862,23 +882,24 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
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break;
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}
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ARMSimplifyRegOffset(Base, Offset, VT);
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ARMSimplifyAddress(Addr, VT);
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// addrmode5 output depends on the selection dag addressing dividing the
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// offset by 4 that it then later multiplies. Do this here as well.
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if (isFloat)
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Offset /= 4;
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Addr.Offset /= 4;
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// FIXME: The 'needReg0Op' bit goes away once STRH is converted to
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// not use the mega-addrmode stuff.
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if (!needReg0Op)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Base).addImm(Offset));
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.addReg(SrcReg).addReg(Addr.Base.Reg).addImm(Addr.Offset));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
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.addReg(SrcReg).addReg(Addr.Base.Reg)
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.addReg(0).addImm(Addr.Offset));
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return true;
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}
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@ -898,14 +919,13 @@ bool ARMFastISel::SelectStore(const Instruction *I) {
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return false;
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// Our register and offset with innocuous defaults.
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unsigned Base = 0;
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int Offset = 0;
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Address Addr;
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// See if we can handle this as Reg + Offset
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if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
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if (!ARMComputeAddress(I->getOperand(1), Addr))
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return false;
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if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
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if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
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return true;
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}
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@ -1475,10 +1495,12 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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} else {
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assert(VA.isMemLoc());
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// Need to store on the stack.
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unsigned Base = ARM::SP;
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int Offset = VA.getLocMemOffset();
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Address Addr;
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Addr.BaseType = Address::RegBase;
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Addr.Base.Reg = ARM::SP;
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Addr.Offset = VA.getLocMemOffset();
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if (!ARMEmitStore(ArgVT, Arg, Base, Offset)) return false;
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if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
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}
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}
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return true;
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