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https://github.com/c64scene-ar/llvm-6502.git
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Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
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parent
a0908d0a44
commit
0d82fe77f2
lib/Target/X86
test/MC
@ -21,20 +21,25 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
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def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret",
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"ret",
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[(X86retflag 0)], IIC_RET>;
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[(X86retflag 0)], IIC_RET>;
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def RETW : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{w}",
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[], IIC_RET>, OpSize;
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def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret\t$amt",
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"ret\t$amt",
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[(X86retflag timm:$amt)], IIC_RET_IMM>;
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[(X86retflag timm:$amt)], IIC_RET_IMM>;
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def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"retw\t$amt",
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"ret{w}\t$amt",
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[], IIC_RET_IMM>, OpSize;
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[], IIC_RET_IMM>, OpSize;
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def LRETL : I <0xCB, RawFrm, (outs), (ins),
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def LRETL : I <0xCB, RawFrm, (outs), (ins),
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"lretl", [], IIC_RET>;
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"{l}ret{l|f}", [], IIC_RET>;
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def LRETW : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{w|f}", [], IIC_RET>, OpSize;
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def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
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def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
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"lretq", [], IIC_RET>;
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"{l}ret{q|f}", [], IIC_RET>;
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def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"lret\t$amt", [], IIC_RET>;
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"{l}ret{l|f}\t$amt", [], IIC_RET>;
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def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"lretw\t$amt", [], IIC_RET>, OpSize;
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"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
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}
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}
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// Unconditional branches.
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// Unconditional branches.
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@ -99,3 +99,9 @@
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# CHECK: iretq
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# CHECK: iretq
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0x48 0xcf
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0x48 0xcf
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# CHECK: ret
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0x66 0xc3
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# CHECK: retf
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0x66 0xcb
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@ -42,3 +42,16 @@ LBB0_3:
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// CHECK: encoding: [0x0f,0xc2,0xd1,0x01]
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// CHECK: encoding: [0x0f,0xc2,0xd1,0x01]
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cmpltps XMM2, XMM1
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cmpltps XMM2, XMM1
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// CHECK: encoding: [0xc3]
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ret
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// CHECK: encoding: [0xcb]
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retf
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// CHECK: encoding: [0xc2,0x08,0x00]
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ret 8
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// CHECK: encoding: [0xca,0x08,0x00]
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retf 8
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@ -990,3 +990,11 @@ xchgl %ecx, %eax
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// CHECK: xchgl %ecx, %eax
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// CHECK: xchgl %ecx, %eax
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// CHECK: encoding: [0x91]
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// CHECK: encoding: [0x91]
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xchgl %eax, %ecx
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xchgl %eax, %ecx
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// CHECK: retw
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// CHECK: encoding: [0x66,0xc3]
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retw
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// CHECK: lretw
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// CHECK: encoding: [0x66,0xcb]
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lretw
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@ -50,6 +50,9 @@
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// CHECK: ret
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// CHECK: ret
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ret
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ret
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// CHECK: retw
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retw
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// FIXME: Check that this matches SUB32ri8
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// FIXME: Check that this matches SUB32ri8
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// CHECK: subl $1, %eax
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// CHECK: subl $1, %eax
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subl $1, %eax
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subl $1, %eax
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@ -841,6 +844,7 @@ iretq
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lretq // CHECK: lretq # encoding: [0x48,0xcb]
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lretq // CHECK: lretq # encoding: [0x48,0xcb]
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lretl // CHECK: lretl # encoding: [0xcb]
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lretl // CHECK: lretl # encoding: [0xcb]
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lret // CHECK: lretl # encoding: [0xcb]
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lret // CHECK: lretl # encoding: [0xcb]
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lretw // CHECK: lretw # encoding: [0x66,0xcb]
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// rdar://8403907
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// rdar://8403907
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sysret
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sysret
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