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[ARM64] Move register/register MOV handling into tablegen and improve diagnostics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208527 91177308-0d34-0410-b5e6-96231b3b80d8
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e7dd13a094
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0d919c62c4
lib/Target/ARM64
@ -430,8 +430,14 @@ def logical_imm64_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(enc, MVT::i32);
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}]>;
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def LogicalImm32Operand : AsmOperandClass { let Name = "LogicalImm32"; }
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def LogicalImm64Operand : AsmOperandClass { let Name = "LogicalImm64"; }
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def LogicalImm32Operand : AsmOperandClass {
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let Name = "LogicalImm32";
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let DiagnosticType = "LogicalSecondSource";
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}
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def LogicalImm64Operand : AsmOperandClass {
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let Name = "LogicalImm64";
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let DiagnosticType = "LogicalSecondSource";
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}
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def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
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return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 32);
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}], logical_imm32_XFORM> {
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@ -474,6 +474,15 @@ def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
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defm ADD : AddSub<0, "add", add>;
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defm SUB : AddSub<1, "sub">;
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def : InstAlias<"mov $dst, $src",
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(ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
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def : InstAlias<"mov $dst, $src",
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(ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
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def : InstAlias<"mov $dst, $src",
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(ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
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def : InstAlias<"mov $dst, $src",
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(ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
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defm ADDS : AddSubS<0, "adds", ARM64add_flag, "cmn">;
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defm SUBS : AddSubS<1, "subs", ARM64sub_flag, "cmp">;
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@ -648,6 +657,9 @@ defm ORN : LogicalReg<0b01, 1, "orn",
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BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
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defm ORR : LogicalReg<0b01, 0, "orr", or>;
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def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
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def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
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def : InstAlias<"tst $src1, $src2",
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(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
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def : InstAlias<"tst $src1, $src2",
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@ -152,6 +152,9 @@ def GPR64sp : RegisterClass<"ARM64", [i64], 64, (add GPR64common, SP)> {
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let AltOrderSelect = [{ return 1; }];
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}
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def GPR32sponly : RegisterClass<"ARM64", [i32], 32, (add WSP)>;
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def GPR64sponly : RegisterClass<"ARM64", [i64], 64, (add SP)>;
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// GPR register classes which include WZR/XZR AND SP/WSP. This is not a
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// constraint used by any instructions, it is used as a common super-class.
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def GPR32all : RegisterClass<"ARM64", [i32], 32, (add GPR32common, WZR, WSP)>;
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@ -3945,42 +3945,6 @@ static void rewriteMOVI(ARM64AsmParser::OperandVector &Operands,
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delete Op;
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}
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static void rewriteMOVRSP(ARM64AsmParser::OperandVector &Operands,
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MCContext &Context) {
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ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
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ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
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Operands[0] =
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ARM64Operand::CreateToken("add", false, Op->getStartLoc(), Context);
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const MCExpr *Imm = MCConstantExpr::Create(0, Context);
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Operands.push_back(ARM64Operand::CreateShiftedImm(Imm, 0, Op2->getStartLoc(),
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Op2->getEndLoc(), Context));
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delete Op;
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}
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static void rewriteMOVR(ARM64AsmParser::OperandVector &Operands,
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MCContext &Context) {
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ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[0]);
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ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
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Operands[0] =
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ARM64Operand::CreateToken("orr", false, Op->getStartLoc(), Context);
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// Operands[2] becomes Operands[3].
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Operands.push_back(Operands[2]);
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// And Operands[2] becomes ZR.
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unsigned ZeroReg = ARM64::XZR;
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if (ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(
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Operands[2]->getReg()))
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ZeroReg = ARM64::WZR;
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Operands[2] =
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ARM64Operand::CreateReg(ZeroReg, false, Op2->getStartLoc(),
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Op2->getEndLoc(), Context);
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delete Op;
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}
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bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
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switch (ErrCode) {
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case Match_MissingFeature:
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@ -3999,6 +3963,8 @@ bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
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case Match_AddSubSecondSource:
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return Error(Loc,
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"expected compatible register, symbol or integer in range [0, 4095]");
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case Match_LogicalSecondSource:
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return Error(Loc, "expected compatible register or logical immediate");
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case Match_AddSubRegShift32:
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return Error(Loc,
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"expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]");
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@ -4081,7 +4047,6 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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// FIXME: Catching this here is a total hack, and we should use tblgen
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// support to implement this instead as soon as it is available.
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ARM64Operand *Op1 = static_cast<ARM64Operand *>(Operands[1]);
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ARM64Operand *Op2 = static_cast<ARM64Operand *>(Operands[2]);
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if (Op2->isImm()) {
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op2->getImm())) {
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@ -4130,21 +4095,6 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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else if ((NVal & 0xFFFF000000000000ULL) == NVal)
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rewriteMOVI(Operands, "movn", NVal, 48, getContext());
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}
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} else if (Op1->isReg() && Op2->isReg()) {
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// reg->reg move.
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unsigned Reg1 = Op1->getReg();
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unsigned Reg2 = Op2->getReg();
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if ((Reg1 == ARM64::SP &&
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ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(Reg2)) ||
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(Reg2 == ARM64::SP &&
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ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(Reg1)) ||
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(Reg1 == ARM64::WSP &&
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ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(Reg2)) ||
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(Reg2 == ARM64::WSP &&
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ARM64MCRegisterClasses[ARM64::GPR32allRegClassID].contains(Reg1)))
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rewriteMOVRSP(Operands, getContext());
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else
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rewriteMOVR(Operands, getContext());
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}
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} else if (NumOperands == 4) {
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if (NumOperands == 4 && Tok == "lsl") {
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@ -4523,6 +4473,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_AddSubRegExtendSmall:
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case Match_AddSubRegExtendLarge:
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case Match_AddSubSecondSource:
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case Match_LogicalSecondSource:
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case Match_AddSubRegShift32:
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case Match_AddSubRegShift64:
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case Match_InvalidMemoryIndexed8:
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