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Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Goodwin
2009-09-30 00:10:16 +00:00
parent 6deec348a8
commit 0dad89fa94
11 changed files with 30 additions and 16 deletions
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10
lib/CodeGen/LLVMTargetMachine.cpp
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@@ -45,14 +45,6 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
// This is not enabled by default due to 1) high compile time cost, 2) it's not
// beneficial to all targets. The plan is to let targets decide whether this
// is enabled.
static cl::opt<bool>
EnablePostRAScheduler("post-RA-scheduler",
cl::desc("Enable scheduling after register allocation"),
cl::init(false));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// able to enable or disable fast-isel independently from -O0.
@@ -326,7 +318,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM);
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
if (OptLevel != CodeGenOpt::None) {
PM.add(createPostRAScheduler());
printAndVerify(PM);
}