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[ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207399 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu 2014-04-28 07:34:27 +00:00
parent 7d811a53de
commit 0ddc7447d9
2 changed files with 23 additions and 2 deletions
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6
lib/Target/ARM64/ARM64InstrFormats.td
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@ -6868,10 +6868,12 @@ multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
FPR64, FPR64, vecshiftL64, asm,
[(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn),
(i32 vecshiftL64:$imm)))]> {
[(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
let Inst{21-16} = imm{5-0};
}
def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
(!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
}
multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {

19
test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s
; Check if sqshl/uqshl with constant shift amout can be selected.
define i64 @test_vqshld_s64_i(i64 %a) {
; CHECK-LABEL: test_vqshld_s64_i:
; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
%1 = tail call i64 @llvm.arm64.neon.sqshl.i64(i64 %a, i64 36)
ret i64 %1
}
define i64 @test_vqshld_u64_i(i64 %a) {
; CHECK-LABEL: test_vqshld_u64_i:
; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
%1 = tail call i64 @llvm.arm64.neon.uqshl.i64(i64 %a, i64 36)
ret i64 %1
}
declare i64 @llvm.arm64.neon.uqshl.i64(i64, i64)
declare i64 @llvm.arm64.neon.sqshl.i64(i64, i64)