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Compute feature bits at time of MCSubtargetInfo initialization.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-07-07 07:07:08 +00:00
parent cbd40f8357
commit 0ddff1b535
33 changed files with 159 additions and 108 deletions
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29
include/llvm/MC/MCSubtargetInfo.h
View File

@@ -34,30 +34,29 @@ class MCSubtargetInfo {
const unsigned *ForwardingPathes; // Forwarding pathes
unsigned NumFeatures; // Number of processor features
unsigned NumProcs; // Number of processors
unsigned FeatureBits; // Feature bits for current CPU
public:
void InitMCSubtargetInfo(const SubtargetFeatureKV *PF,
void InitMCSubtargetInfo(StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *PI, const InstrStage *IS,
const unsigned *OC, const unsigned *FP,
unsigned NF, unsigned NP) {
ProcFeatures = PF;
ProcDesc = PD;
ProcItins = PI;
Stages = IS;
OperandCycles = OC;
ForwardingPathes = FP;
NumFeatures = NF;
NumProcs = NP;
unsigned NF, unsigned NP);
/// getFeatureBits - Get the feature bits.
///
uint64_t getFeatureBits() const {
return FeatureBits;
}
/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
/// feature string), recompute and return feature bits.
uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
///
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
/// getFeatureBits - Get the feature bits for a CPU (optionally supplemented
/// with feature string).
uint64_t getFeatureBits(StringRef CPU, StringRef FS) const;
};
} // End llvm namespace

19
include/llvm/Target/TargetRegistry.h
View File

@@ -70,7 +70,9 @@ namespace llvm {
StringRef TT);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(void);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
StringRef CPU,
StringRef Features);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &CPU,
@@ -269,10 +271,18 @@ namespace llvm {
/// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
///
MCSubtargetInfo *createMCSubtargetInfo() const {
/// \arg Triple - This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
/// \arg CPU - This specifies the name of the target CPU.
/// \arg Features - This specifies the string representation of the
/// additional target features.
MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
StringRef Features) const {
if (!MCSubtargetInfoCtorFn)
return 0;
return MCSubtargetInfoCtorFn();
return MCSubtargetInfoCtorFn(Triple, CPU, Features);
}
/// createTargetMachine - Create a target specific machine implementation
@@ -824,7 +834,8 @@ namespace llvm {
TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
}
private:
static MCSubtargetInfo *Allocator() {
static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
StringRef FS) {
return new MCSubtargetInfoImpl();
}
};

40
lib/MC/MCSubtargetInfo.cpp
View File

@@ -16,6 +16,38 @@
using namespace llvm;
void MCSubtargetInfo::InitMCSubtargetInfo(StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *PI,
const InstrStage *IS,
const unsigned *OC,
const unsigned *FP,
unsigned NF, unsigned NP) {
ProcFeatures = PF;
ProcDesc = PD;
ProcItins = PI;
Stages = IS;
OperandCycles = OC;
ForwardingPathes = FP;
NumFeatures = NF;
NumProcs = NP;
SubtargetFeatures Features(FS);
FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
ProcFeatures, NumFeatures);
}
/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
/// feature string) and recompute feature bits.
uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
SubtargetFeatures Features(FS);
FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
ProcFeatures, NumFeatures);
return FeatureBits;
}
InstrItineraryData
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
assert(ProcItins && "Instruction itineraries information not available!");
@@ -42,11 +74,3 @@ MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
return InstrItineraryData(Stages, OperandCycles, ForwardingPathes,
(InstrItinerary *)Found->Value);
}
/// getFeatureBits - Get the feature bits for a CPU (optionally supplemented
/// with feature string).
uint64_t MCSubtargetInfo::getFeatureBits(StringRef CPU, StringRef FS) const {
SubtargetFeatures Features(FS);
return Features.getFeatureBits(CPU, ProcDesc, NumProcs,
ProcFeatures, NumFeatures);
}

38
lib/MC/SubtargetFeature.cpp
View File

@@ -231,8 +231,9 @@ uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
size_t CPUTableSize,
const SubtargetFeatureKV *FeatureTable,
size_t FeatureTableSize) {
assert(CPUTable && "missing CPU table");
assert(FeatureTable && "missing features table");
if (!FeatureTableSize || !CPUTableSize)
return 0;
#ifndef NDEBUG
for (size_t i = 1; i < CPUTableSize; i++) {
assert(strcmp(CPUTable[i - 1].Key, CPUTable[i].Key) < 0 &&
@@ -249,24 +250,27 @@ uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
if (CPU == "help")
Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize);
// Find CPU entry
const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize);
// If there is a match
if (CPUEntry) {
// Set base feature bits
Bits = CPUEntry->Value;
// Find CPU entry if CPU name is specified.
if (!CPU.empty()) {
const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize);
// If there is a match
if (CPUEntry) {
// Set base feature bits
Bits = CPUEntry->Value;
// Set the feature implied by this CPU feature, if any.
for (size_t i = 0; i < FeatureTableSize; ++i) {
const SubtargetFeatureKV &FE = FeatureTable[i];
if (CPUEntry->Value & FE.Value)
SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize);
// Set the feature implied by this CPU feature, if any.
for (size_t i = 0; i < FeatureTableSize; ++i) {
const SubtargetFeatureKV &FE = FeatureTable[i];
if (CPUEntry->Value & FE.Value)
SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize);
}
} else {
errs() << "'" << CPU
<< "' is not a recognized processor for this target"
<< " (ignoring processor)\n";
}
} else {
errs() << "'" << CPU
<< "' is not a recognized processor for this target"
<< " (ignoring processor)\n";
}
// Iterate through each feature
for (size_t i = 0, E = Features.size(); i < E; i++) {
const StringRef Feature = Features[i];

10
lib/Target/ARM/ARMSubtarget.cpp
View File

@@ -38,7 +38,7 @@ StrictAlign("arm-strict-align", cl::Hidden,
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
: ARMGenSubtargetInfo()
: ARMGenSubtargetInfo(TT, CPU, FS)
, ARMProcFamily(Others)
, HasV4TOps(false)
, HasV5TOps(false)
@@ -78,9 +78,6 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
if (CPUString.empty())
CPUString = "generic";
if (TT.find("eabi") != std::string::npos)
TargetABI = ARM_ABI_AAPCS;
// Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied
// based on the architecture version.
@@ -92,7 +89,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
ArchFS = FS;
}
ParseSubtargetFeatures(ArchFS, CPUString);
ParseSubtargetFeatures(CPUString, ArchFS);
// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
// ARM version or CPU and then remove this.
@@ -105,6 +102,9 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
// After parsing Itineraries, set ItinData.IssueWidth.
computeIssueWidth();
if (TT.find("eabi") != std::string::npos)
TargetABI = ARM_ABI_AAPCS;
if (isAAPCS_ABI())
stackAlignment = 8;

3
lib/Target/ARM/ARMSubtarget.h
View File

@@ -25,6 +25,7 @@
namespace llvm {
class GlobalValue;
class StringRef;
class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
@@ -168,7 +169,7 @@ protected:
}
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void computeIssueWidth();

5
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@@ -40,9 +40,10 @@ MCRegisterInfo *createARMMCRegisterInfo() {
return X;
}
MCSubtargetInfo *createARMMCSubtargetInfo() {
MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitARMMCSubtargetInfo(X);
InitARMMCSubtargetInfo(X, CPU, FS);
return X;
}

4
lib/Target/Alpha/AlphaSubtarget.cpp
View File

@@ -23,13 +23,13 @@ using namespace llvm;
AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
: AlphaGenSubtargetInfo(), HasCT(false) {
: AlphaGenSubtargetInfo(TT, CPU, FS), HasCT(false) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);

3
lib/Target/Alpha/AlphaSubtarget.h
View File

@@ -22,6 +22,7 @@
#include "AlphaGenSubtargetInfo.inc"
namespace llvm {
class StringRe;
class AlphaSubtarget : public AlphaGenSubtargetInfo {
protected:
@@ -39,7 +40,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool hasCT() const { return HasCT; }
};

4
lib/Target/Blackfin/BlackfinSubtarget.cpp
View File

@@ -23,7 +23,7 @@ using namespace llvm;
BlackfinSubtarget::BlackfinSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS)
: BlackfinGenSubtargetInfo(), sdram(false),
: BlackfinGenSubtargetInfo(TT, CPU, FS), sdram(false),
icplb(false),
wa_mi_shift(false),
wa_csync(false),
@@ -39,5 +39,5 @@ BlackfinSubtarget::BlackfinSubtarget(const std::string &TT,
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
}

4
lib/Target/Blackfin/BlackfinSubtarget.h
View File

@@ -21,6 +21,7 @@
#include "BlackfinGenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class BlackfinSubtarget : public BlackfinGenSubtargetInfo {
bool sdram;
@@ -40,8 +41,7 @@ namespace llvm {
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // end namespace llvm

4
lib/Target/CellSPU/SPUSubtarget.cpp
View File

@@ -25,7 +25,7 @@ using namespace llvm;
SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS) :
SPUGenSubtargetInfo(),
SPUGenSubtargetInfo(TT, CPU, FS),
StackAlignment(16),
ProcDirective(SPU::DEFAULT_PROC),
UseLargeMem(false)
@@ -35,7 +35,7 @@ SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
std::string default_cpu("v0");
// Parse features string.
ParseSubtargetFeatures(FS, default_cpu);
ParseSubtargetFeatures(default_cpu, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(default_cpu);

3
lib/Target/CellSPU/SPUSubtarget.h
View File

@@ -23,6 +23,7 @@
namespace llvm {
class GlobalValue;
class StringRef;
namespace SPU {
enum {
@@ -57,7 +58,7 @@ namespace llvm {
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.

4
lib/Target/MBlaze/MBlazeSubtarget.cpp
View File

@@ -26,7 +26,7 @@ using namespace llvm;
MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS):
MBlazeGenSubtargetInfo(),
MBlazeGenSubtargetInfo(TT, CPU, FS),
HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
HasFPU(false), HasMul64(false), HasSqrt(false)
{
@@ -34,7 +34,7 @@ MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "mblaze";
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
// Only use instruction scheduling if the selected CPU has an instruction
// itinerary (the default CPU is the only one that doesn't).

3
lib/Target/MBlaze/MBlazeSubtarget.h
View File

@@ -22,6 +22,7 @@
#include "MBlazeGenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class MBlazeSubtarget : public MBlazeGenSubtargetInfo {
@@ -46,7 +47,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// Compute the number of maximum number of issues per cycle for the
/// MBlaze scheduling itineraries.

9
lib/Target/MSP430/MSP430Subtarget.cpp
View File

@@ -22,10 +22,11 @@
using namespace llvm;
MSP430Subtarget::MSP430Subtarget(const std::string &TT,
const std::string &CPUIgnored,
const std::string &FS) {
std::string CPU = "generic";
const std::string &CPU,
const std::string &FS) :
MSP430GenSubtargetInfo(TT, CPU, FS) {
std::string CPUName = "generic";
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
ParseSubtargetFeatures(CPUName, FS);
}

3
lib/Target/MSP430/MSP430Subtarget.h
View File

@@ -22,6 +22,7 @@
#include <string>
namespace llvm {
class StringRef;
class MSP430Subtarget : public MSP430GenSubtargetInfo {
bool ExtendedInsts;
@@ -34,7 +35,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // End llvm namespace

4
lib/Target/Mips/MipsSubtarget.cpp
View File

@@ -23,7 +23,7 @@ using namespace llvm;
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little) :
MipsGenSubtargetInfo(),
MipsGenSubtargetInfo(TT, CPU, FS),
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
@@ -35,7 +35,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
MipsArchVersion = Mips1;
// Parse features string.
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);

3
lib/Target/Mips/MipsSubtarget.h
View File

@@ -22,6 +22,7 @@
#include "MipsGenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class MipsSubtarget : public MipsGenSubtargetInfo {
@@ -99,7 +100,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isMips1() const { return MipsArchVersion == Mips1; }
bool isMips32() const { return MipsArchVersion >= Mips32; }

4
lib/Target/PTX/PTXSubtarget.cpp
View File

@@ -23,7 +23,7 @@ using namespace llvm;
PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
: PTXGenSubtargetInfo(),
: PTXGenSubtargetInfo(TT, CPU, FS),
PTXTarget(PTX_COMPUTE_1_0),
PTXVersion(PTX_VERSION_2_0),
SupportsDouble(false),
@@ -32,7 +32,7 @@ PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU,
std::string TARGET = CPU;
if (TARGET.empty())
TARGET = "generic";
ParseSubtargetFeatures(FS, TARGET);
ParseSubtargetFeatures(TARGET, FS);
}
std::string PTXSubtarget::getTargetString() const {

5
lib/Target/PTX/PTXSubtarget.h
View File

@@ -20,6 +20,8 @@
#include "PTXGenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class PTXSubtarget : public PTXGenSubtargetInfo {
public:
@@ -112,8 +114,7 @@ namespace llvm {
(PTXTarget >= PTX_COMPUTE_2_0 && PTXTarget < PTX_LAST_COMPUTE);
}
void ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
}; // class PTXSubtarget
} // namespace llvm

4
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@@ -64,7 +64,7 @@ static const char *GetCurrentPowerPCCPU() {
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
: PPCGenSubtargetInfo()
: PPCGenSubtargetInfo(TT, CPU, FS)
, StackAlignment(16)
, DarwinDirective(PPC::DIR_NONE)
, IsGigaProcessor(false)
@@ -88,7 +88,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
#endif
// Parse features string.
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);

4
lib/Target/PowerPC/PPCSubtarget.h
View File

@@ -26,6 +26,7 @@
#undef PPC
namespace llvm {
class StringRef;
namespace PPC {
// -m directive values.
@@ -80,8 +81,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.

4
lib/Target/Sparc/SparcSubtarget.cpp
View File

@@ -22,7 +22,7 @@ using namespace llvm;
SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit) :
SparcGenSubtargetInfo(),
SparcGenSubtargetInfo(TT, CPU, FS),
IsV9(false),
V8DeprecatedInsts(false),
IsVIS(false),
@@ -39,5 +39,5 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
IsV9 = CPUName == "v9";
// Parse features string.
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
}

3
lib/Target/Sparc/SparcSubtarget.h
View File

@@ -21,6 +21,7 @@
#include "SparcGenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
bool IsV9;
@@ -38,7 +39,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool is64Bit() const { return Is64Bit; }
std::string getDataLayout() const {

4
lib/Target/SystemZ/SystemZSubtarget.cpp
View File

@@ -26,13 +26,13 @@ using namespace llvm;
SystemZSubtarget::SystemZSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS):
SystemZGenSubtargetInfo(), HasZ10Insts(false) {
SystemZGenSubtargetInfo(TT, CPU, FS), HasZ10Insts(false) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "z9";
// Parse features string.
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
}
/// True if accessing the GV requires an extra load.

3
lib/Target/SystemZ/SystemZSubtarget.h
View File

@@ -22,6 +22,7 @@
namespace llvm {
class GlobalValue;
class StringRef;
class TargetMachine;
class SystemZSubtarget : public SystemZGenSubtargetInfo {
@@ -35,7 +36,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isZ10() const { return HasZ10Insts; }

5
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@@ -40,9 +40,10 @@ MCRegisterInfo *createX86MCRegisterInfo() {
return X;
}
MCSubtargetInfo *createX86MCSubtargetInfo() {
MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitX86MCSubtargetInfo(X);
InitX86MCSubtargetInfo(X, CPU, FS);
return X;
}

4
lib/Target/X86/X86Subtarget.cpp
View File

@@ -292,7 +292,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS,
bool is64Bit, unsigned StackAlignOverride)
: X86GenSubtargetInfo()
: X86GenSubtargetInfo(TT, CPU, FS)
, PICStyle(PICStyles::None)
, X86SSELevel(NoMMXSSE)
, X863DNowLevel(NoThreeDNow)
@@ -320,7 +320,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = sys::getHostCPUName();
ParseSubtargetFeatures(FS, CPUName);
ParseSubtargetFeatures(CPUName, FS);
// All X86-64 CPUs also have SSE2, however user might request no SSE via
// -mattr, so don't force SSELevel here.
if (HasAVX)

3
lib/Target/X86/X86Subtarget.h
View File

@@ -24,6 +24,7 @@
namespace llvm {
class GlobalValue;
class StringRef;
class TargetMachine;
/// PICStyles - The X86 backend supports a number of different styles of PIC.
@@ -135,7 +136,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
/// instruction.

2
lib/Target/XCore/XCoreSubtarget.cpp
View File

@@ -23,6 +23,6 @@ using namespace llvm;
XCoreSubtarget::XCoreSubtarget(const std::string &TT,
const std::string &CPU, const std::string &FS)
: XCoreGenSubtargetInfo()
: XCoreGenSubtargetInfo(TT, CPU, FS)
{
}

3
lib/Target/XCore/XCoreSubtarget.h
View File

@@ -22,6 +22,7 @@
#include "XCoreGenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class XCoreSubtarget : public XCoreGenSubtargetInfo {
@@ -34,7 +35,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // End llvm namespace

27
utils/TableGen/SubtargetEmitter.cpp
View File

@@ -605,8 +605,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
<< "// subtarget options.\n"
<< "void llvm::";
OS << Target;
OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
<< " const std::string &CPU) {\n"
OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
<< " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
<< " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n";
@@ -615,11 +614,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
return;
}
OS << " SubtargetFeatures Features(FS);\n"
<< " uint64_t Bits = Features.getFeatureBits(CPU, "
<< Target << "SubTypeKV, " << NumProcs << ",\n"
<< " " << Target << "FeatureKV, "
<< NumFeatures << ");\n";
OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n";
for (unsigned i = 0; i < Features.size(); i++) {
// Next record
@@ -629,10 +624,12 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
const std::string &Attribute = R->getValueAsString("Attribute");
if (Value=="true" || Value=="false")
OS << " if ((Bits & " << Target << "::" << Instance << ") != 0) "
OS << " if ((Bits & " << Target << "::"
<< Instance << ") != 0) "
<< Attribute << " = " << Value << ";\n";
else
OS << " if ((Bits & " << Target << "::" << Instance << ") != 0 && "
OS << " if ((Bits & " << Target << "::"
<< Instance << ") != 0 && "
<< Attribute << " < " << Value << ") "
<< Attribute << " = " << Value << ";\n";
}
@@ -663,8 +660,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
// MCInstrInfo initialization routine.
OS << "static inline void Init" << Target
<< "MCSubtargetInfo(MCSubtargetInfo *II) {\n";
OS << " II->InitMCSubtargetInfo(";
<< "MCSubtargetInfo(MCSubtargetInfo *II, StringRef CPU, StringRef FS) {\n";
OS << " II->InitMCSubtargetInfo(CPU, FS, ";
if (NumFeatures)
OS << Target << "FeatureKV, ";
else
@@ -702,7 +699,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
std::string ClassName = Target + "GenSubtargetInfo";
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
<< " explicit " << ClassName << "();\n"
<< " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
<< "StringRef FS);\n"
<< "};\n";
OS << "} // End llvm namespace \n";
@@ -712,9 +710,10 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "#undef GET_SUBTARGETINFO_CTOR\n";
OS << "namespace llvm {\n";
OS << ClassName << "::" << ClassName << "()\n"
OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
<< "StringRef FS)\n"
<< " : TargetSubtargetInfo() {\n"
<< " InitMCSubtargetInfo(";
<< " InitMCSubtargetInfo(CPU, FS, ";
if (NumFeatures)
OS << Target << "FeatureKV, ";
else