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Add encoding support for Thumb2 PLD and PLI instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-11-30 19:19:31 +00:00
parent 06a86da323
commit 0e1bcdf4f7
4 changed files with 45 additions and 1 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -183,6 +183,8 @@ namespace {
const { return 0; }
unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
const { return 0; }
unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)

24
lib/Target/ARM/ARMInstrThumb2.td
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@ -146,6 +146,11 @@ def t2am_imm8_offset : Operand<i32>,
string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
}
def t2am_imm12_offset : Operand<i32> {
string EncoderMethod = "getT2AddrModeImm12OffsetOpValue";
}
// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
def t2addrmode_imm8s4 : Operand<i32> {
let PrintMethod = "printT2AddrModeImm8s4Operand";
@ -1539,6 +1544,10 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let Inst{21} = write;
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
bits<16> addr;
let Inst{19-16} = addr{15-12}; // Rn
let Inst{11-0} = addr{11-0}; // imm12
}
def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
@ -1552,6 +1561,10 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
let Inst{11-8} = 0b1100;
bits<13> addr;
let Inst{19-16} = addr{12-9}; // Rn
let Inst{7-0} = addr{7-0}; // imm8
}
def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
@ -1565,10 +1578,15 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
let Inst{11-6} = 0000000;
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
let Inst{5-4} = addr{1-0}; // imm2
}
let isCodeGenOnly = 1 in
def pci : T2Ipc<(outs), (ins i32imm:$addr), IIC_Preload, opc,
def pci : T2Ipc<(outs), (ins t2am_imm12_offset:$addr), IIC_Preload, opc,
"\t$addr",
[]> {
let Inst{31-25} = 0b1111100;
@ -1579,6 +1597,10 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let Inst{20} = 1;
let Inst{19-16} = 0b1111; // Rn = 0b1111
let Inst{15-12} = 0b1111;
bits<13> addr;
let Inst{23} = addr{12};
let Inst{11-0} = addr{11-0};
}
}

18
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -183,6 +183,8 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const;
@ -722,6 +724,22 @@ getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
return Value;
}
unsigned ARMMCCodeEmitter::
getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO1 = MI.getOperand(OpNum);
// FIXME: Needs fixup support.
unsigned Value = 0;
int32_t tmp = (int32_t)MO1.getImm();
if (tmp < 0)
tmp = abs(tmp);
else
Value |= 4096; // Set the ADD bit
Value |= tmp & 4095;
return Value;
}
unsigned ARMMCCodeEmitter::
getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const {

2
utils/TableGen/EDEmitter.cpp
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@ -614,6 +614,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
MISC("it_mask", "kOperandTypeThumbITMask"); // I
MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
MISC("t2am_imm12_offset", "kOperandTypeThumb2AddrModeImm12Offset");//I
MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
@ -840,6 +841,7 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
operandTypes.addEntry("kOperandTypeThumb2SoImm");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12Offset");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");