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Allow FP arguments pass / return

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 14:19:16 +00:00
parent 2c97ae8826
commit 0e31d5cf80
2 changed files with 39 additions and 21 deletions
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11
lib/Target/SystemZ/SystemZCallingConv.td
View File

@ -17,7 +17,11 @@ def RetCC_SystemZ : CallingConv<[
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// i64 is returned in register R2 // i64 is returned in register R2
CCIfType<[i64], CCAssignToReg<[R2D]>> CCIfType<[i64], CCAssignToReg<[R2D]>>,
// f32 / f64 are returned in F0
CCIfType<[f32], CCAssignToReg<[F0S]>>,
CCIfType<[f64], CCAssignToReg<[F0L]>>
]>; ]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -31,6 +35,11 @@ def CC_SystemZ : CallingConv<[
// integer registers. // integer registers.
CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>, CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
// The first 4 ifloating point arguments of non-varargs functions are passed
// in FP registers.
CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
CCIfType<[f64], CCAssignToReg<[F0L, F2L, F4L, F6L]>>,
// Integer values get stored in stack slots that are 8 bytes in // Integer values get stored in stack slots that are 8 bytes in
// size and 8-byte aligned. // size and 8-byte aligned.
CCIfType<[i64], CCAssignToStack<8, 8>> CCIfType<[i64], CCAssignToStack<8, 8>>

49
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -173,33 +173,42 @@ SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
if (VA.isRegLoc()) { if (VA.isRegLoc()) {
// Arguments passed in registers // Arguments passed in registers
MVT RegVT = VA.getLocVT(); MVT RegVT = VA.getLocVT();
TargetRegisterClass *RC;
switch (RegVT.getSimpleVT()) { switch (RegVT.getSimpleVT()) {
default: default:
cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
<< RegVT.getSimpleVT() << RegVT.getSimpleVT()
<< "\n"; << "\n";
abort(); abort();
case MVT::i64: case MVT::i64:
unsigned VReg = RC = SystemZ::GR64RegisterClass;
RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass); break;
RegInfo.addLiveIn(VA.getLocReg(), VReg); case MVT::f32:
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT); RC = SystemZ::FP32RegisterClass;
break;
// If this is an 8/16/32-bit value, it is really passed promoted to 64 case MVT::f64:
// bits. Insert an assert[sz]ext to capture this, then truncate to the RC = SystemZ::FP64RegisterClass;
// right size. break;
if (VA.getLocInfo() == CCValAssign::SExt)
ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::ZExt)
ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
if (VA.getLocInfo() != CCValAssign::Full)
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
ArgValues.push_back(ArgValue);
} }
unsigned VReg = RegInfo.createVirtualRegister(RC);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
// If this is an 8/16/32-bit value, it is really passed promoted to 64
// bits. Insert an assert[sz]ext to capture this, then truncate to the
// right size.
if (VA.getLocInfo() == CCValAssign::SExt)
ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::ZExt)
ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
if (VA.getLocInfo() != CCValAssign::Full)
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
ArgValues.push_back(ArgValue);
} else { } else {
// Sanity check // Sanity check
assert(VA.isMemLoc()); assert(VA.isMemLoc());