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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-05-02 20:38:34 +00:00
Move LiveUnionArray into LiveIntervalUnion.h
It is useful outside RegAllocBase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158041 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -208,3 +208,26 @@ bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
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VRI = VirtReg->advanceTo(VRI, Overlaps.start());
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VRI = VirtReg->advanceTo(VRI, Overlaps.start());
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}
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}
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}
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}
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void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc,
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unsigned NSize) {
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// Reuse existing allocation.
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if (NSize == Size)
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return;
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clear();
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Size = NSize;
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LIUs = static_cast<LiveIntervalUnion*>(
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malloc(sizeof(LiveIntervalUnion)*NSize));
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for (unsigned i = 0; i != Size; ++i)
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new(LIUs + i) LiveIntervalUnion(Alloc);
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}
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void LiveIntervalUnion::Array::clear() {
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if (!LIUs)
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return;
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for (unsigned i = 0; i != Size; ++i)
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LIUs[i].~LiveIntervalUnion();
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free(LIUs);
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Size = 0;
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LIUs = 0;
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}
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@ -181,6 +181,28 @@ public:
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Query(const Query&); // DO NOT IMPLEMENT
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Query(const Query&); // DO NOT IMPLEMENT
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void operator=(const Query&); // DO NOT IMPLEMENT
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void operator=(const Query&); // DO NOT IMPLEMENT
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};
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};
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// Array of LiveIntervalUnions.
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class Array {
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unsigned Size;
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LiveIntervalUnion *LIUs;
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public:
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Array() : Size(0), LIUs(0) {}
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~Array() { clear(); }
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// Initialize the array to have Size entries.
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// Reuse an existing allocation if the size matches.
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void init(LiveIntervalUnion::Allocator&, unsigned Size);
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unsigned size() const { return Size; }
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void clear();
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LiveIntervalUnion& operator[](unsigned idx) {
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assert(idx < Size && "idx out of bounds");
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return LIUs[idx];
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}
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};
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -52,10 +52,11 @@ bool RegAllocBase::VerifyEnabled = false;
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void RegAllocBase::verify() {
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void RegAllocBase::verify() {
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LiveVirtRegBitSet VisitedVRegs;
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LiveVirtRegBitSet VisitedVRegs;
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OwningArrayPtr<LiveVirtRegBitSet>
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OwningArrayPtr<LiveVirtRegBitSet>
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unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
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unionVRegs(new LiveVirtRegBitSet[TRI->getNumRegs()]);
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// Verify disjoint unions.
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// Verify disjoint unions.
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for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
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for (unsigned PhysReg = 0, NumRegs = TRI->getNumRegs(); PhysReg != NumRegs;
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++PhysReg) {
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DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
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DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
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LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
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LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
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PhysReg2LiveUnion[PhysReg].verify(VRegs);
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PhysReg2LiveUnion[PhysReg].verify(VRegs);
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@ -89,16 +90,6 @@ void RegAllocBase::verify() {
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// RegAllocBase Implementation
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// RegAllocBase Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instantiate a LiveIntervalUnion for each physical register.
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void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
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unsigned NRegs) {
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NumRegs = NRegs;
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Array =
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static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
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for (unsigned r = 0; r != NRegs; ++r)
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new(Array + r) LiveIntervalUnion(allocator);
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}
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
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NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
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TRI = &vrm.getTargetRegInfo();
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TRI = &vrm.getTargetRegInfo();
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@ -109,25 +100,15 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
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RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
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const unsigned NumRegs = TRI->getNumRegs();
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const unsigned NumRegs = TRI->getNumRegs();
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if (NumRegs != PhysReg2LiveUnion.numRegs()) {
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if (NumRegs != PhysReg2LiveUnion.size()) {
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PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
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PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
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// Cache an interferece query for each physical reg
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// Cache an interferece query for each physical reg
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Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
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Queries.reset(new LiveIntervalUnion::Query[NumRegs]);
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}
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}
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}
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}
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void RegAllocBase::LiveUnionArray::clear() {
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if (!Array)
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return;
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for (unsigned r = 0; r != NumRegs; ++r)
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Array[r].~LiveIntervalUnion();
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free(Array);
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NumRegs = 0;
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Array = 0;
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}
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void RegAllocBase::releaseMemory() {
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void RegAllocBase::releaseMemory() {
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for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r)
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for (unsigned r = 0, e = PhysReg2LiveUnion.size(); r != e; ++r)
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PhysReg2LiveUnion[r].clear();
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PhysReg2LiveUnion[r].clear();
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}
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}
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@ -253,7 +234,8 @@ void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
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return;
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return;
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LiveIntervalUnion::SegmentIter SI;
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LiveIntervalUnion::SegmentIter SI;
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for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
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for (unsigned PhysReg = 0, NumRegs = TRI->getNumRegs(); PhysReg != NumRegs;
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++PhysReg) {
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LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
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LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
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if (LiveUnion.empty())
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if (LiveUnion.empty())
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continue;
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continue;
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@ -62,27 +62,7 @@ class RegAllocBase {
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// registers may have changed.
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// registers may have changed.
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unsigned UserTag;
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unsigned UserTag;
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// Array of LiveIntervalUnions indexed by physical register.
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LiveIntervalUnion::Array PhysReg2LiveUnion;
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class LiveUnionArray {
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unsigned NumRegs;
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LiveIntervalUnion *Array;
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public:
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LiveUnionArray(): NumRegs(0), Array(0) {}
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~LiveUnionArray() { clear(); }
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unsigned numRegs() const { return NumRegs; }
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void init(LiveIntervalUnion::Allocator &, unsigned NRegs);
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void clear();
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LiveIntervalUnion& operator[](unsigned PhysReg) {
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assert(PhysReg < NumRegs && "physReg out of bounds");
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return Array[PhysReg];
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}
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};
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LiveUnionArray PhysReg2LiveUnion;
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// Current queries, one per physreg. They must be reinitialized each time we
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// Current queries, one per physreg. They must be reinitialized each time we
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// query on a new live virtual register.
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// query on a new live virtual register.
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